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参数资料
| 型号： | P89V51RD2FA,512 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 61/80页 |
| 文件大小： | 0K |
| 描述： | IC 80C51 MCU FLASH 64K 44-PLCC |
| 产品培训模块： | Migrating from 8/16-Bit MCUs to 32-Bit ARMs |
| 标准包装： | 26 |
| 系列： | 89V |
| 核心处理器： | 8051 |
| 芯体尺寸： | 8-位 |
| 速度： | 40MHz |
| 连通性： | SPI，UART/USART |
| 外围设备： | 欠压检测/复位，POR，PWM，WDT |
| 输入/输出数： | 32 |
| 程序存储器容量： | 64KB（64K x 8） |
| 程序存储器类型： | 闪存 |
| RAM 容量： | 1K x 8 |
| 电压 - 电源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振荡器型： | 内部 |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 44-LCC（J 形引线） |
| 包装： | 管件 |
| 产品目录页面： | 706 (CN2011-ZH PDF) |
| 配用： | 622-1017-ND - BOARD 44-ZIF PLCC SOCKET 622-1001-ND - USB IN-CIRCUIT PROG 80C51ISP |
| 其它名称： | 568-1290-5 935276046512 P89V51RD2FA |
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PIC18F87K22 FAMILY
DS39960D-page 64
2009-2011 Microchip Technology Inc.
4.4.3
RC_IDLE MODE
In RC_IDLE mode, the CPU is disabled but the periph-
erals continue to be clocked from the internal oscillator
block using the INTOSC multiplexer. This mode
provides controllable power conservation during Idle
periods.
From RC_RUN, this mode is entered by setting the
IDLEN bit and executing a SLEEP instruction. If the
device is in another Run mode, first set IDLEN, then set
the SCS1 bit and execute SLEEP. To maintain software
compatibility with future devices, it is recommended
that SCS0 also be cleared, though its value is ignored.
The INTOSC multiplexer may be used to select a
higher clock frequency by modifying the IRCF bits
before executing the SLEEP instruction. When the
clock source is switched to the INTOSC multiplexer, the
primary oscillator is shut down and the OSTS bit is
cleared.
If the IRCF bits are set to any non-zero value, or the
INTSRC/MFIOSEL bit is set, the INTOSC output is
enabled. The HFIOFS/MFIOFS bits become set, after
the INTOSC output becomes stable, after an interval of
on the HFIOFS/MFIOFS bits, see Table 4-3.)
Clocks to the peripherals continue while the INTOSC
source stabilizes. The HFIOFS/MFIOFS bits will
remain set if the IRCF bits were previously at a non-
zero value or if INTSRC was set before the SLEEP
instruction was executed and the INTOSC source was
already stable. If the IRCF bits and INTSRC are all
clear, the INTOSC output will not be enabled, the
HFIOFS/MFIOFS bits will remain clear and there will be
no indication of the current clock source.
When a wake event occurs, the peripherals continue to
be clocked from the INTOSC multiplexer. After a delay
wake event, the CPU begins executing code clocked
by the INTOSC multiplexer. The IDLEN and SCS bits
are not affected by the wake-up. The INTRC source will
continue to run if either the WDT or the Fail-Safe Clock
Monitor is enabled.
4.5
Selective Peripheral Module
Control
Idle mode allows users to substantially reduce power
consumption by stopping the CPU clock. Even so,
peripheral modules still remain clocked, and thus,
consume power. There may be cases where the appli-
cation needs what this mode does not provide: the
allocation of power resources to the CPU processing
with minimal power consumption from the peripherals.
PIC18F87K22 family devices address this requirement
by allowing peripheral modules to be selectively
disabled,
reducing
or
eliminating
their
power
consumption. This can be done with two control bits:
Peripheral Enable bit, generically named XXXEN –
Located in the respective module’s main control
register
Peripheral Module Disable (PMD) bit, generically
named, XXXMD – Located in one of the PMDx
Control registers (PMD0, PMD1, PMD2 or PMD3)
Disabling a module by clearing its XXXEN bit disables
the module’s functionality, but leaves its registers
available to be read and written to. This reduces power
consumption, but not by as much as the second
approach.
Most peripheral modules have an enable bit.
In contrast, setting the PMD bit for a module disables
all clock sources to that module, reducing its power
consumption to an absolute minimum. In this state, the
control and status registers associated with the periph-
eral are also disabled, so writes to those registers have
no effect and read values are invalid. Many peripheral
modules have a corresponding PMD bit.
There are four PMD registers in the PIC18F87K22 family
devices: PMD0, PMD1, PMD2 and PMD3. These
registers have bits associated with each module for
disabling or enabling a particular peripheral.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| P89V51RD2FBC | 制造商:NXP Semiconductors 功能描述: |
| P89V51RD2FBC,557 | 功能描述:8位微控制器 -MCU 80C51 64K FL / 1K RM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| P89V51RD2FBC557 | 制造商:NXP 功能描述: |
| P89V51RD2FN | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:8-bit 80C51 5 V low power 16/32/64 kB flash microcontroller with 1 kB RAM |
| P89V51RD2FN,112 | 功能描述:8位微控制器 -MCU 80C51 64K FL / 1K RM RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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