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参数资料
| 型号： | PBA31301/2S |
| 厂商： | ERICSSON POWER MODULES AB |
| 元件分类： | 通信及网络 |
| 英文描述： | SPECIALTY TELECOM CIRCUIT, CBGA34 |
| 封装： | 10.20 X 14 X 1.60 MM, BGA-34 |
| 文件页数： | 11/12页 |
| 文件大小： | 812K |
| 代理商： | PBA31301/2S |
8
PBA 313 01
EN/LZT 146 65 R3B Ericsson Microelectronics AB, October 2001
Table 4. Description of registers.
Delay
bit 7:
Delay PHD_OFF negative edge 6 us.
bit 6:
Delay SYNT_ON negative edge 6 us..
bit 5-3:
Reserved.
Channel
bit 7:
RX/TX
- Receive (1) or Transmit (0) channel
bit 6-0:
Channel value - 0 - 127 decimal
RSSI
bit 4-0:
Received signal strength indicator, lower input power
gives lower RSSI value.
XO-trim
bit 5-0:
Trim value for the internal capacitor load of the crystal
(0 = 0 pF, 63 = 8 pF)
ID
bit 7-4:
Chip identity, Radio Controller = 0001.
bit 3-0:
Chip version number.
LPOLO
bit 7-0:
Eight least significant bits of the LPO frequency
adjust value (LPO7-LPO0). LPO8:0 = 0 gives maxi-
mum fLPO and 511 mininum fLPO.
LPOHI
bit 0:
Most significant bit of the LPO adjust value (LPO8).
Control
bit 6-3:
LPO coarse trimming, lower value gives higher fLPO.
bit 2:
Crystal oscillator control. After POR has been acti-
vated, a 0 to 1 transition enables the SYS_CLK_REQ
control pin.
Modulation
bit 6-4:
TX modulation amplitude. 0 gives 10% higher than
the nominal value, 7 gives 10% lower.
bit 3-0:
Reserved.
Current
bit 7-5:
Reserved.
Enable
bit 7-6:
Reserved
bit 5-1:
Amplifier power control. 00000=On, 11111=Off.
bit 0:
Polarity of TX_DATA. 1 = positive, 0 = negative
polarity.
Serial Interface
The serial control interface is a JTAG Boundary-Scan Archi-
tecture (IEEE Std 1149.1). Interconnection between the serial
interface and the external controller (baseband circuit) con-
sists of four 1-bit digital signals; control data input (SI_CDI),
control mode select (SI_CMS), control clock (SI_CLK) and
control data output (SI_CDO). The timing of these signals are
defined in figure 8.
State Diagram
The serial interface (SI) is operational when POR is 'high'.
The state diagram is shown in figure 9. Transitions from one
state to another depend on the SI_CMS input at the rising
edge of SI_CLK. The SI controller is normally kept in the Run-
Control/Idle state. SI_CMS and SI_CDI should change value
at the falling edge of SI_CLK. The SI_CDO output will also
change at the falling edge of SI_CLK.
Four types of instruction registers (table 3) can be accessed in
an IR-Scan. Performing an IR-Scan with IR=01YYYY selects
one of the data register in the radio. Reference source not
found. IR starting with the bit code 11 allows serial data
to be by-passed from SI_CDI to SI_CDO. The EXTEST and
SAMPLE/PRELOAD instructions have no action.
IR
Description
00
EXTEST (no action)
01YYY
Selection of a Data Register
10
SAMPLE/PRELOAD (no action)
11
BYPASS
Table 3. Instruction registers.
Data register scans (DR-Scan) transfer 8 bits data from the
readable register at address 01YYYY to SI_TDO, and 8 bits
of data from SI_TDI to the writable register at the same
address, in one single operation. See figure 10. Table 5 lists
the different registers in the radio controller, their read or write
operation, address, and content after a reset. The functiona-
lity is described in table 4.
Figure 9. State machine for serial interface control. '0' denotes
a logic level 'low' and '1' level 'high' level on the SI_CMS
control pin.
Control-
Logic-Reset
Run Con-
trol/Idle
Select-DR-
Scan
Capture-
DR
Shift-DR
Exit1-DR
Pause-DR
Exit2-DR
Update-DR
0
1
0
1
0
1
0
1
0
1
0
1
0
Select-IR-
Scan
Capture-IR
Shift-IR
Exit1-IR
Pause-IR
Exit2-IR
Update-IR
1
0
1
0
1
0
1
0
1
0
1
Figure 8. Timing diagram of the serial interface.
Min Typ
Max
Unit
tSI_CLK
200
250
ns
tSI_CLK2
76
ns
t1
20
ns
t2
20
ns
SI_ CLK
SI _CDI
SI _CDO
SI_ CMS
t2
tSI_CLK
t1
tSI_CLK2
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