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参数资料
| 型号： | PC13892AJVL |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| 封装： | 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-186 |
| 文件页数： | 33/67页 |
| 文件大小： | 2571K |
| 代理商： | PC13892AJVL |
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Table 9. Power Up Sequence
Tap x 2.0 ms
PUMS2 = OPEN (I,MX37,i.MX51)
PUMS2 = GND (i.MX35,i.MX27)
0
SW2
1
SW4
VGEN2
2
VIOHI
SW4
3
VGEN2
VIOHI, VSD
4
SW1
SWBST, VUSB(35)
5
SW3
SW1
6
VPLL
7
VDIG
SW3
8
VDIG
9
VUSB(34), VUSB2
VUSB2
Notes
32.
Time slots may be included for blocks which are defined by the PUMS pins as disabled, to allow for potential activation.
33.
The following supplies are not included in the matrix, since they are not intended for activation by the start-up sequencer: VCAM,
VGEN1, VGEN3, VVIDEO, and VAUDIO. SWBST is not included on the PUMS2 = Open column
34.
USB supplies VUSB, is only enabled if 5.0 V is present on UVBUS.
35.
SWBST = 5.0 V, powers up, as does VUSB, regardless of the 5.0 V present on UVBUS. By default VUSB will be supplied by SWBST.
Analog Integrated Circuit Device Data
Freescale Semiconductor
39
13892
FUNCTIONAL DESCRIPTION
FUNCTIONAL PIN DESCRIPTION
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
MODE
USB LBP mode, normal mode, test mode selection & anti-
fuse bias. During evaluation and testing, the IC can be
configured for normal operation or test mode via the MODE
pin as summarized in the following table.
MODE PIN STATE
MODE
Ground
Normal Operation
VCOREDIG
USB Low Power Boot Allowed
VCORE
Test Mode
GNDCTRL
Ground for control logic.
SPIVCC
Supply for SPI bus and audio bus
CS
CS held low at Cold Start configures the interface for SPI
mode. Once activated, CS functions as the SPI Chip Select.
CS tied to VCORE at Cold Start configures the interface for
I2C mode; the pin is not used in I2C mode other than for
configuration.
Because the SPI interface pins can be reconfigured for
reuse as an I2C interface, a configuration protocol mandates
that the CS pin is held low during a turn on event for the IC (a
weak pull-down is integrated on the CS pin).
CLK
Primary SPI clock input. In I2C mode, this pin is the SCL
signal (I2C bus clock).
MOSI
Primary SPI write input. In I2C mode, the MOSI pin hard
wired to ground or VCORE is used to select between two
possible addresses (A0 address selection).
MISO
Primary SPI read output. In I2C mode, this pin is the SDA
signal (bi-directional serial data line).
GNDSPI
Ground for SPI interface.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC13892AJVLR2 | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Tape and Reel |
| PC13892BJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
| PC13892JVK | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Bulk |
| PC13892JVK/R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Power Management and User Interface IC |
| PC13892JVKR2 | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Tape and Reel |
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