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参数资料
| 型号： | PC13892AJVL |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 电源管理 |
| 英文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PBGA186 |
| 封装： | 12 X 12 MM, 0.80 MM PITCH, ROHS COMPLIANT, PLASTIC, MABGA-186 |
| 文件页数： | 50/67页 |
| 文件大小： | 2571K |
| 代理商： | PC13892AJVL |
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Analog Integrated Circuit Device Data
54
Freescale Semiconductor
13892
FUNCTIONAL DEVICE OPERATION
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are not
available from Freescale for import or sale in the United States prior to September 2010: MC13892*VK and MC13892*VL in 139, 186 MAPBGA packages.
CHRGISNS, and the current through the external sense
resistor connected between CHRGISNS and BPSNS. When
required, a duty cycle is applied to the FETs connected on
CHRGCTRL1 and CHRGCTRL2, and thus the charge
current, in order to stay within the power budget. At the same
time the FET connected to BATTFET pin is forced to conduct
to keep the application powered. In case of excessive supply
conditions, the power limiter minimum duty cycle may not be
sufficiently small to maintain the actual power dissipation
within budget. In that case, the charge path will be disabled
and the CHGFAULTI interrupt generated.
The power budget can be programmed by the SPI through
the PLIM[1:0] bits, which establishes a power limit from 600
to 1200 mW in 200 mV steps. The power dissipation limiter
can be disabled by setting the PLIMDIS bit. In this case, it is
advised to use close software control to estimate the
dissipated power in the external pass FETs. The power
limiter is automatically disabled in serial path factory mode
and in reverse mode.
Since a charger attachment can be a Turn On event when
a product is initially in the Off state, any nondefault settings
that are intended for PLIM[1:0] and PLIMDIS should be
programmed early in the configuration sequence to ensure
proper supply conditions adapted to the application. To avoid
any false detection during power up, the power limiter output
is blanked at the start of the charge cycle. As a safety
precaution, the power dissipation is monitored and the
desired duty cycle is estimated. When this estimated duty
cycle falls below the power limiter minimum duty cycle, the
charger circuit will be disabled.
ADC SUBSYSTEM
The ADC core is a 10 bit converter. The ADC core and
logic run on 2/3 of the switcher PLL generated frequency, so
approximately 2.0 MHz. If an ADC conversion is requested
while the PLL is not active, it will be automatically enabled by
the ADC. A 32.768 kHz equivalent time base is derived from
the 2.0 MHz clock to time ADC events. The ADC is supplied
from VCORE. The ADC core has an integrated auto
calibration circuit which reduces the offset and gain errors.
The switcher PLL is programmable, so when the switcher
frequency is changed, the frequency applied to the ADC
converter will change accordingly. Although the conversion
time is inversely proportional to the PLLX[2:0] setting, this will
not influence the ADC performance. The locally derived
32.768 kHz will remain constant in order to not influence the
different timings depending on this time base.
The ADC Subsystem has 8 channels:
Channel 0 Battery Voltage:
The battery voltage is read at the BATT pin at channel 0.
Channel 1 Battery Current:
The current flowing out of and into the battery can be read
via the ADC by monitoring the voltage drop over the sense
resistor between BATT and BATTISNSCC.
Channel 2 Application Supply:
The application supply voltage is read at the BP pin at
channel 2.
Channel 3 Charger Voltage:
The charger voltage is measured at the CHRGRAW pin at
channel 3.
Channel 4 Charger Current:
The charge current is read by monitoring the voltage drop
over the charge current sense resistor. This resistor is
connected between CHRGISNS and BPSNS.
Channel 5 ADIN5, Battery Thermistor and Battery Detect:
On channel 5, ADIN5 may be used as a general purpose
input, but in a typical application, ADIN5 is used to read out
the battery pack thermistor. The thermistor will have to be
biased with an external pull-up to a voltage rail greater than
the ADC input range. In order to save current when the
thermistor reading is not required, it can be biased from one
of the general purpose IOs such as GPO1. A resistor divider
network should assure the resulting voltage falls within the
ADC input range, especially when the thermistor check
function is used.
When the application is on and supplied by the charger, a
battery removal can be detected by a battery thermistor
presence check. When the thermistor terminal becomes
high-impedance, the battery is considered being removed.
This detection function is available at the ADIN5 input.
Channel 6 ADIN6 and Coin Cell Voltage:
On channel 6, ADIN6 may be used as a general purpose
unscaled input but in a typical application, the PA thermistor
is connected here. In addition, on channel 6, the voltage of
the coin cell connected to the LICELL pin can be read.
Channel 7 ADIN7 and ADIN7B, UID and Die Temperature:
On channel 7, ADIN7 may be used as a general purpose
input. In a typical application, an ambient light sensor is
connected here. A second general purpose input ADIN7B is
available. In the application, a second ambient light sensor is
supposed to be connected here.
In addition, on channel 7, the voltage of the USB ID line
connected to the UID pin and the die temperature can be
read.
COULOMB COUNTER
As discussed previously, the current into and from the
battery can be read out through the general purpose ADC as
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC13892AJVLR2 | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Tape and Reel |
| PC13892BJVL | 制造商:Freescale Semiconductor 功能描述:5/28V BCK/BST PMUIC - Trays |
| PC13892JVK | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Bulk |
| PC13892JVK/R2 | 制造商:FREESCALE 制造商全称:Freescale Semiconductor, Inc 功能描述:Power Management and User Interface IC |
| PC13892JVKR2 | 制造商:Freescale Semiconductor 功能描述:POWER MGMT IC - Tape and Reel |
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