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参数资料
| 型号： | PC16550D |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | PC16550D通用异步接收器/发射器与FIFO的 |
| 文件页数： | 16/22页 |
| 文件大小： | 344K |
| 代理商： | PC16550D |
8.0
Bit 7:
This bit is the Divisor Latch Access Bit (DLAB). It must
be set high (logic 1) to access the Divisor Latches of the
Baud Generator during a Read or Write operation. It must
be set low (logic 0) to access the Receiver Buffer, the
Transmitter Holding Register, or the Interrupt Enable Regis-
ter.
Registers
(Continued)
8.2
TYPICAL CLOCK CIRCUITS
TL/C/8652–19
TL/C/8652–20
Typical Crystal Oscillator Network
(Note)
CRYSTAL
R
P
1 M
X
R
X2
1.5k
C
1
C
2
3.1 MHz
10-30 pF
40-60 pF
1.8 MHz
1 M
X
1.5k
10-30 pF
40-60 pF
Note:
These R and C values are approximate and may vary 2x depending
on the crystal characteristics. All crystal circuits should be designed
specifically for the system.
8.3
PROGRAMMABLE BAUD GENERATOR
The UART contains a programmable Baud Generator that is
capable of taking any clock input from DC to 24 MHz and
dividing it by any divisor from 2 to 2
16
b
1. The output fre-
quency of the Baud Generator is 16
c
the Baud
[
divisor
Y
e
(frequency input)
d
(baud rate
c
16)
]
. Two 8-bit latches
store the divisor in a 16-bit binary format. These Divisor
Latches must be loaded during initialization to ensure prop-
er operation of the Baud Generator. Upon loading either of
the Divisor Latches, a 16-bit Baud counter is immediately
loaded.
Table III provides decimal divisors to use with crystal fre-
quencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz, re-
spectively. For baud rates of 38400 and below, the error
obtained is minimal. The accuracy of the desired baud rate
is dependent on the crystal frequency chosen. Using a divi-
sor of zero is
not
recommended.
8.4
LINE STATUS REGISTER
This register provides status information to the CPU con-
cerning the data transfer. Table II shows the contents of the
Line Status Register. Details on each bit follow.
Bit 0:
This bit is the receiver Data Ready (DR) indicator. Bit
0 is set to a logic 1 whenever a complete incoming charac-
ter has been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a logic 0 by
reading all of the data in the Receiver Buffer Register or the
FIFO.
Bit 1:
This bit is the Overrun Error (OE) indicator. Bit 1 indi-
cates that data in the Receiver Buffer Register was not read
by the CPU before the next character was transferred into
the Receiver Buffer Register, thereby destroying the previ-
ous character. The OE indicator is set to a logic 1 upon
detection of an overrun condition and reset whenever the
CPU reads the contents of the Line Status Register. If the
FIFO mode data continues to fill the FIFO beyond the trig-
ger level, an overrun error will occur only after the FIFO is
full and the next character has been completely received in
the shift register. OE is indicated to the CPU as soon as it
happens. The character in the shift register is overwritten,
but it is not transferred to the FIFO.
Bit 2:
This bit is the Parity Error (PE) indicator. Bit 2 indi-
cates that the received data character does not have the
correct even or odd parity, as selected by the even-parity-
select bit. The PE bit is set to a logic 1 upon detection of a
parity error and is reset to a logic 0 whenever the CPU reads
the contents of the Line Status Register. In the FIFO mode
this error is associated with the particular character in the
FIFO it applies to. This error is revealed to the CPU when its
associated character is at the top of the FIFO.
Bit 3:
This bit is the Framing Error (FE) indicator. Bit 3 indi-
cates that the received character did not have a valid Stop
bit. Bit 3 is set to a logic 1 whenever the Stop bit following
the last data bit or parity bit is detected as a logic 0 bit
(Spacing level). The FE indicator is reset whenever the CPU
reads the contents of the Line Status Register. In the FIFO
mode this error is associated with the particular character in
the FIFO it applies to. This error is revealed to the CPU
when its associated character is at the top of the FIFO. The
UART will try to resynchronize after a framing error. To do
this it assumes that the framing error was due to the next
start bit, so it samples this ‘‘start’’ bit twice and then takes in
the ‘‘data’’.
Bit 4:
This bit is the Break Interrupt (BI) indicator. Bit 4 is set
to a logic 1 whenever the received data input is held in the
Spacing (logic 0) state for longer than a full word transmis-
sion time (that is, the total time of Start bit
a
data bits
a
Parity
a
Stop bits). The BI indicator is reset whenever the
CPU reads the contents of the Line Status Register. In the
FIFO mode this error is associated with the particular char-
acter in the FIFO it applies to. This error is revealed to the
CPU when its associated character is at the top of the FIFO.
When break occurs only one zero character is loaded into
the FIFO. The next character transfer is enabled after SIN
goes to the marking state and receives the next valid start
bit.
Note:
Bits 1 through 4 are the error conditions that produce a Receiver Line
Status interrupt whenever any of the corresponding conditions are
detected and the interrupt is enabled.
16
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相关代理商/技术参数 |
参数描述 |
|---|---|
| PC16550DN | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DN | 制造商:Texas Instruments 功能描述:IC CMOS UART FIFO 6550 DIP40 |
| PC16550DN/NOPB | 功能描述:UART 接口集成电路 UNIV ASYNCHRONOUS RCVR/TRANS W/ FIFO RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DV | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DV/NOPB | 功能描述:UART 接口集成电路 UART W/ FIFO IN PCC RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
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