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参数资料
| 型号： | PC16550DV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 1/22页 |
| 文件大小： | 344K |
| 代理商： | PC16550DV |
TL/C/8652
P
June 1995
PC16550D Universal Asynchronous
Receiver/Transmitter with FIFOs
2
General Description
The PC16550D is an improved version of the original 16450
Universal
Asynchronous
Receiver/Transmitter
Functionally identical to the 16450 on powerup (CHARAC-
TER mode)
*
the PC16550D can be put into an alternate
mode (FIFO mode) to relieve the CPU of excessive software
overhead.
(UART).
In this mode internal FIFOs are activated allowing 16 bytes
(plus 3 bits of error data per byte in the RCVR FIFO) to be
stored in both receive and transmit modes. All the logic is on
chip to minimize system overhead and maximize system ef-
ficiency. Two pin functions have been changed to allow sig-
nalling of DMA transfers.
The UART performs serial-to-parallel conversion on data
characters received from a peripheral device or a MODEM,
and parallel-to-serial conversion on data characters re-
ceived from the CPU. The CPU can read the complete
status of the UART at any time during the functional opera-
tion. Status information reported includes the type and con-
dition of the transfer operations being performed by the
UART, as well as any error conditions (parity, overrun, fram-
ing, or break interrupt).
The UART includes a programmable baud rate generator
that is capable of dividing the timing reference clock input
by divisors of 1 to (2
16
b
1), and producing a 16
c
clock for
driving the internal transmitter logic. Provisions are also in-
cluded to use this 16
c
clock to drive the receiver logic. The
UART has complete MODEM-control capability, and a proc-
essor-interrupt system. Interrupts can be programmed to
the user’s requirements, minimizing the computing required
to handle the communications link.
The UART is fabricated using National Semiconductor’s ad-
vanced M
2
CMOS process.
*
Can also be reset to 16450 Mode under software control.
2
Note: This part is patented.
Features
Y
Capable of running all existing 16450 software.
Y
Pin for pin compatible with the existing 16450 except
for CSOUT (24) and NC (29). The former CSOUT and
NC pins are TXRDY and RXRDY, respectively.
Y
After reset, all registers are identical to the 16450 reg-
ister set.
Y
In the FIFO mode transmitter and receiver are each
buffered with 16 byte FIFO’s to reduce the number of
interrrupts presented to the CPU.
Y
Adds or deletes standard asynchronous communication
bits (start, stop, and parity) to or from the serial data.
Y
Holding and shift registers in the 16450 Mode eliminate
the need for precise synchronization between the CPU
and serial data.
Y
Independently controlled transmit, receive, line status,
and data set interrupts.
Y
Programmable baud generator divides any input clock
by 1 to (2
16
b
1) and generates the 16
c
clock.
Y
Independent receiver clock input.
Y
MODEM control functions (CTS, RTS, DSR, DTR, RI,
and DCD).
Y
Fully programmable serial-interface characteristics:
D 5-, 6-, 7-, or 8-bit characters
D Even, odd, or no-parity bit generation and detection
D 1-, 1
(/2
-, or 2-stop bit generation
D Baud generation (DC to 1.5M baud).
Y
False start bit detection.
Y
Complete status reporting capabilities.
Y
TRI-STATE
é
TTL drive for the data and control buses.
Y
Line break generation and detection.
Y
Internal diagnostic capabilities:
D Loopback controls for communications link fault
isolation
D Break, parity, overrun, framing error simulation.
Y
Full prioritized interrupt system controls.
Basic Configuration
TL/C/8652–1
TRI-STATE
é
is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
RRD-B30M75/Printed in U. S. A.
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| PC16552C | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
| PC16552CV | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
| PC16552D | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
| PC16552DV | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
| PC16553 | WRISTLOCK TERMINAL |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PC16550DV/NOPB | 功能描述:UART 接口集成电路 UART W/ FIFO IN PCC RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVEF | 制造商:Texas Instruments 功能描述: |
| PC16550DVX | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVX/NOPB | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16552C | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
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