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参数资料
| 型号： | PC16550DV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 11/22页 |
| 文件大小： | 344K |
| 代理商： | PC16550DV |
6.0 Pin Descriptions
The following describes the function of all UART pins. Some
of these descriptions reference internal circuits.
In the following descriptions, a low represents a logic 0 (0V
nominal) and a high represents a logic 1 (
a
2.4V nominal).
A0, A1, A2,
Register Select, Pins 26–28: Address signals
connected to these 3 inputs select a UART register for the
CPU to read from or write to during data transfer. A table of
registers and their addresses is shown below. Note that the
state of the Divisor Latch Access Bit (DLAB), which is the
most significant bit of the Line Control Register, affects the
selection of certain UART registers. The DLAB must be set
high by the system software to access the Baud Generator
Divisor Latches.
Register Addresses
DLAB
A
2
A
1
A
0
Register
0
0
0
0
Receiver Buffer (read),
Transmitter Holding
Register (write)
Interrupt Enable
Interrupt Identification (read)
FIFO Control (write)
Line Control
MODEM Control
Line Status
MODEM Status
Scratch
Divisor Latch
(least significant byte)
Divisor Latch
(most significant byte)
0
X
X
X
X
X
X
X
1
0
0
0
0
1
1
1
1
0
0
1
1
1
0
0
1
1
0
1
0
0
1
0
1
0
1
0
1
0
0
1
ADS,
Address Strobe, Pin 25: The positive edge of an active
Address Strobe (ADS) signal latches the Register Select
(A0, A1, A2) and Chip Select (CS0, CS1, CS2) signals.
Note:
An active ADS input is required when the Register Select (A0, A1, A2)
and Chip Select (CS0, CS1, CS2) signals are not stable for the dura-
tion of a read or write operation. If not required, tie the ADS input
permanently low.
BAUDOUT,
Baud Out, Pin 15: This is the 16
c
clock signal
from the transmitter section of the UART. The clock rate is
equal to the main reference oscillator frequency divided by
the specified divisor in the Baud Generator Divisor Latches.
The BAUDOUT may also be used for the receiver section by
tying this output to the RCLK input of the chip.
CS0, CS1, CS2,
Chip Select, Pins 12–14: When CS0 and
CS1 are high and CS2 is low, the chip is selected. This
enables communication between the UART and the CPU.
The positive edge of an active Address Strobe signal latch-
es the decoded chip select signals, completing chip selec-
tion. If ADS is always low, valid chip selects should stabilize
according to the t
CSW
parameter.
CTS,
Clear to Send, Pin 36: When low, this indicates that
the MODEM or data set is ready to exchange data. The CTS
signal is a MODEM status input whose conditions can be
tested by the CPU reading bit 4 (CTS) of the MODEM Status
Register. Bit 4 is the complement of the CTS signal. Bit 0
(DCTS) of the MODEM Status Register indicates whether
the CTS input has changed state since the previous reading
of the MODEM Status Register. CTS has no effect on the
Transmitter.
Note:
Whenever the CTS bit of the MODEM Status Register changes state,
an interrupt is generated if the MODEM Status Interrupt is enabled.
D
7
–D
0
,
Data Bus, Pins 1–8: This bus comprises eight TRI-
STATE input/output lines. The bus provides bidirectional
communications between the UART and the CPU. Data,
control words, and status information are transferred via the
D
7
–D
0
Data Bus.
DCD,
Data Carrier Detect, Pin 38: When low, indicates that
the data carrier has been detected by the MODEM or data
set. The DCD signal is a MODEM status input whose condi-
tion can be tested by the CPU reading bit 7 (DCD) of the
MODEM Status Register. Bit 7 is the complement of the
DCD signal. Bit 3 (DDCD) of the MODEM Status Register
indicates whether the DCD input has changed state since
the previous reading of the MODEM Status Register. DCD
has no effect on the receiver.
Note:
Whenever the DCD bit of the MODEM Status Register changes state,
an interrupt is generated if the MODEM Status Interrupt is enabled.
DDIS,
Driver Disable, Pin 23: This goes low whenever the
CPU is reading data from the UART. It can disable or control
the direction of a data bus transceiver between the CPU
and the UART.
DSR,
Data Set Ready, Pin 37: When low, this indicates that
the MODEM or data set is ready to establish the communi-
cations link with the UART. The DSR signal is a MODEM
status input whose condition can be tested by the CPU
reading bit 5 (DSR) of the MODEM Status Register. Bit 5 is
the complement of the DSR signal. Bit 1 (DDSR) of the
MODEM Status Register indicates whether the DSR input
has changed state since the previous reading of the MO-
DEM Status Register.
Note:
Whenever the DDSR bit of the MODEM Status Register changes
state, an interrupt is generated if the MODEM Status Interrupt is en-
abled.
DTR,
Data Terminal Ready, Pin 33: When low, this informs
the MODEM or data set that the UART is ready to establish
a communications link. The DTR output signal can be set to
an active low by programming bit 0 (DTR) of the MODEM
Control Register to a high level. A Master Reset operation
sets this signal to its inactive (high) state. Loop mode opera-
tion holds this signal in its inactive state.
INTR,
Interrupt, Pin 30: This pin goes high whenever any
one of the following interrupt types has an active high condi-
tion and is enabled via the IER: Receiver Error Flag; Re-
ceived Data Available: timeout (FIFO Mode only); Transmit-
ter Holding Register Empty; and MODEM Status. The INTR
signal is reset low upon the appropriate interrupt service or
a Master Reset operation.
MR,
Master Reset, Pin 35: When this input is high, it clears
all the registers (except the Receiver Buffer, Transmitter
Holding, and Divisor Latches), and the control logic of the
UART. The states of various output signals (SOUT, INTR,
OUT 1, OUT 2, RTS, DTR) are affected by an active MR
input (Refer to Table I.) This input is buffered with a TTL-
compatible Schmitt Trigger with 0.5V typical hysteresis.
OUT 1,
Output 1, Pin 34: This user-designated output can
be set to an active low by programming bit 2 (OUT 1) of the
MODEM Control Register to a high level. A Master Reset
operation sets this signal to its inactive (high) state. Loop
mode operation holds this signal in its inactive state. In the
XMOS parts this will achieve TTL levels.
11
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相关代理商/技术参数 |
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| PC16550DV/NOPB | 功能描述:UART 接口集成电路 UART W/ FIFO IN PCC RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVEF | 制造商:Texas Instruments 功能描述: |
| PC16550DVX | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVX/NOPB | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16552C | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
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