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参数资料
| 型号： | PC16550DV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 17/22页 |
| 文件大小： | 344K |
| 代理商： | PC16550DV |
8.0
Registers
(Continued)
TABLE IV. Interrupt Control Functions
FIFO
Mode
Only
Interrupt
Identification
Register
Interrupt Set and Reset Functions
Bit 3
Bit 2 Bit 1 Bit 0
Priority
Level
Interrupt Type
Interrupt Source
Interrupt Reset Control
0
0
0
1
D
None
None
D
0
1
1
0
Highest Receiver Line Status
Overrun Error or Parity Error or
Framing Error or Break Interrupt
Reading the Line Status
Register
0
1
0
0
Second Received Data Available Receiver Data Available or Trigger
Reading the Receiver Buffer
Register or the FIFO Drops
Below the Trigger Level
Level Reached
1
1
0
0
Second Character Timeout
Indication
No Characters Have Been
Removed From or Input to the
RCVR FIFO During the Last 4 Char.
Times and There Is at Least 1 Char.
in It During This Time
Reading the Receiver
Buffer Register
0
0
1
0
Third
Transmitter Holding
Register Empty
Transmitter Holding
Register Empty
Reading the IIR Register (if
source of interrupt) or Writing
into the Transmitter Holding
Register
0
0
0
0
Fourth
MODEM Status
Clear to Send or Data Set Ready or
Ring Indicator or Data Carrier
Detect
Reading the MODEM
Status Register
Bit 5:
This bit is the Transmitter Holding Register Empty
(THRE) indicator. Bit 5 indicates that the UART is ready to
accept a new character for transmission. In addition, this bit
causes the UART to issue an interrupt to the CPU when the
Transmit Holding Register Empty Interrupt enable is set
high. The THRE bit is set to a logic 1 when a character is
transferred from the Transmitter Holding Register into the
Transmitter Shift Register. The bit is reset to logic 0 concur-
rently with the loading of the Transmitter Holding Register
by the CPU. In the FIFO mode this bit is set when the XMIT
FIFO is empty; it is cleared when at least 1 byte is written to
the XMIT FIFO.
Bit 6:
This bit is the Transmitter Empty (TEMT) indicator. Bit
6 is set to a logic 1 whenever the Transmitter Holding Regis-
ter (THR) and the Transmitter Shift Register (TSR) are both
empty. It is reset to a logic 0 whenever either the THR or
TSR contains a data character. In the FIFO mode this bit is
set to one whenever the transmitter FIFO and shift register
are both empty.
Bit 7:
In the 16450 Mode this is a 0. In the FIFO mode LSR7
is set when there is at least one parity error, framing error or
break indication in the FIFO. LSR7 is cleared when the CPU
reads the LSR, if there are no subsequent errors in the
FIFO.
Note:
The Line Status Register is intended for read operations only. Writing
to this register is not recommended as this operation is only used for
factory testing. In the FIFO mode the software must load a data byte
in the Rx FIFO via Loopback Mode in order to write to LSR2–LSR4.
LSR0 and LSR7 can’t be written to in FIFO mode.
8.5
FIFO CONTROL REGISTER
This is a write only register at the same location as the IIR
(the IIR is a read only register). This register is used to en-
able the FIFOs, clear the FIFOs, set the RCVR FIFO trigger
level, and select the type of DMA signalling.
Bit 0:
Writing a 1 to FCR0 enables both the XMIT and RCVR
FIFOs. Resetting FCR0 will clear all bytes in both FIFOs.
When changing from the FIFO Mode to the 16450 Mode
and vice versa, data is automatically cleared from the
FIFOs. This bit must be a 1 when other FCR bits are written
to or they will not be programmed.
Bit 1:
Writing a 1 to FCR1 clears all bytes in the RCVR FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-clear-
ing.
Bit 2:
Writing a 1 to FCR2 clears all bytes in the XMIT FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is self-clear-
ing.
Bit 3:
Setting FCR3 to a 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1 if FCR0
e
1
(see description of RXRDY and TXRDY pins).
Bit 4, 5:
FCR4 to FCR5 are reserved for future use.
Bit 6, 7:
FCR6 and FCR7 are used to set the trigger level for
the RCVR FIFO interrupt.
7
6
RCVR FIFO
Trigger Level (Bytes)
0
0
1
1
0
1
0
1
01
04
08
14
8.6
INTERRUPT IDENTIFICATION REGISTER
In order to provide minimum software overhead during data
character transfers, the UART prioritizes interrupts into four
levels and records these in the interrupt Identification Regis-
ter. The four levels of interrupt conditions in order of priority
are Receiver Line Status; Received Data Ready; Transmit-
ter Holding Register Empty; and MODEM Status.
17
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相关代理商/技术参数 |
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| PC16550DV/NOPB | 功能描述:UART 接口集成电路 UART W/ FIFO IN PCC RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVEF | 制造商:Texas Instruments 功能描述: |
| PC16550DVX | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVX/NOPB | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16552C | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
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