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参数资料
| 型号： | PC16550DV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | 1 CHANNEL(S), 1.5M bps, SERIAL COMM CONTROLLER, PQCC44 |
| 封装： | PLASTIC, LCC-44 |
| 文件页数： | 12/22页 |
| 文件大小： | 344K |
| 代理商： | PC16550DV |
6.0 Pin Descriptions
(Continued)
OUT 2,
Output 2, Pin 31: This user-designated output that
can be set to an active low by programming bit 3 (OUT 2) of
the MODEM Control Register to a high level. A Master Re-
set operation sets this signal to its inactive (high) state.
Loop mode operation holds this signal in its inactive state. In
the XMOS parts this will achieve TTL levels.
RCLK,
Receiver Clock, Pin 9: This input is the 16
c
baud
rate clock for the receiver section of the chip.
RD, RD,
Read, Pins 22 and 21: When RD is high or RD is
low while the chip is selected, the CPU can read status
information or data from the selected UART register.
Note:
Only an active RD or RD input is required to transfer data from the
UART during a read operation. Therefore, tie either the RD input per-
manently low or the RD input permanently high, when it is not used.
RI,
Ring Indicator, Pin 39: When low, this indicates that a
telephone ringing signal has been received by the MODEM
or data set. The RI signal is a MODEM status input whose
condition can be tested by the CPU reading bit 6 (RI) of the
MODEM Status Register. Bit 6 is the complement of the RI
signal. Bit 2 (TERI) of the MODEM Status Register indicates
whether the RI input
signal
has changed from a low to a
high state since the previous reading of the MODEM Status
Register.
Note:
Whenever the RI
bit
of the MODEM Status Register changes from a
high to a low state, an interrupt is generated if the MODEM Status
Interrupt is enabled.
RTS,
Request to Send, Pin 32: When low, this informs the
MODEM or data set that the UART is ready to exchange
data. The RTS output signal can be set to an active low by
programming bit 1 (RTS) of the MODEM Control Register. A
Master Reset operation sets this signal to its inactive (high)
state. Loop mode operation holds this signal in its inactive
state.
SIN,
Serial Input, Pin 10: Serial data input from the commu-
nications link (peripheral device, MODEM, or data set).
SOUT,
Serial Output, Pin 11: Composite serial data output
to the communications link (peripheral, MODEM or data
set). The SOUT signal is set to the Marking (logic 1) state
upon a Master Reset operation.
TXRDY, RXRDY,
Pins 24, 29: Transmitter and Receiver
DMA signalling is available through two pins (24 and 29).
When operating in the FIFO mode, one of two types of DMA
signalling per pin can be selected via FCR3. When operat-
ing as in the 16450 Mode, only DMA mode 0 is allowed.
Mode 0 supports single transfer DMA where a transfer is
made between CPU bus cycles. Mode 1 supports multi-
transfer DMA where multiple transfers are made continu-
ously until the RCVR FIFO has been emptied or the XMIT
FIFO has been filled.
RXRDY,
Mode 0: When in the 16450 Mode (FCR0
e
0) or in
the FIFO Mode (FCR0
e
1, FCR3
e
0) and there is at least 1
character in the RCVR FIFO or RCVR holding register, the
RXRDY pin (29) will be low active. Once it is activated the
RXRDY pin will go inactive when there are no more charac-
ters in the FIFO or holding register.
RXRDY,
Mode 1: In the FIFO Mode (FCR0
e
1) when the
FCR3
e
1 and the trigger level or the timeout has been
reached, the RXRDY pin will go low active. Once it is acti-
vated it will go inactive when there are no more characters
in the FIFO or holding register.
TXRDY,
Mode 0: In the 16450 Mode (FCR0
e
0) or in the
FIFO Mode (FCR0
e
1, FCR3
e
0) and there are no charac-
ters in the XMIT FIFO or XMIT holding register, the TXRDY
pin (24) will be low active. Once it is activated the TXRDY
pin will go inactive after the first character is loaded into the
XMIT FIFO or holding register.
TXRDY,
Mode 1: In the FIFO Mode (FCR0
e
1) when
FCR3
e
1 and there are no characters in the XMIT FIFO, the
TXRDY pin will go low active. This pin will become inactive
when the XMIT FIFO is completely full.
V
DD
,
Pin 40:
a
5V supply.
V
SS
,
Pin 20: Ground (0V) reference.
WR, WR,
Write, Pins 19 and 18: When WR is high or WR is
low while the chip is selected, the CPU can write control
words or data into the selected UART register.
Note:
Only an active WR or WR input is required to transfer data to the
UART during a write operation. Therefore, tie either the WR input
permanently low or the WR input permanently high, when it is not
used.
XIN
(External Crystal Input), Pin 16: This signal input is used
in conjunction with XOUT to form a feedback circuit for the
baud rate generator’s oscillator. If a clock signal will be gen-
erated off-chip, then it should drive the baud rate generator
through this pin.
XOUT
(External Crystal Output), Pin 17: This signal output is
used in conjunction with XIN to form a feedback circuit for
the baud rate generator’s oscillator. If the clock signal will
be generated off-chip, then this pin is unused.
7.0
Connection Diagrams
Dual-In-Line Package
TL/C/8652–17
Top View
Order Number PC16550DN
See NS Package Number N40A
12
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| PC16552D | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
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相关代理商/技术参数 |
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|---|---|
| PC16550DV/NOPB | 功能描述:UART 接口集成电路 UART W/ FIFO IN PCC RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVEF | 制造商:Texas Instruments 功能描述: |
| PC16550DVX | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16550DVX/NOPB | 功能描述:UART 接口集成电路 RoHS:否 制造商:Texas Instruments 通道数量:2 数据速率:3 Mbps 电源电压-最大:3.6 V 电源电压-最小:2.7 V 电源电流:20 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 封装 / 箱体:LQFP-48 封装:Reel |
| PC16552C | 制造商:NSC 制造商全称:National Semiconductor 功能描述:Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
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