参数资料
型号: PC16550D
厂商: National Semiconductor Corporation
英文描述: PC16550D Universal Asynchronous Receiver/Transmitter with FIFOs
中文描述: PC16550D通用异步接收器/发射器与FIFO的
文件页数: 4/22页
文件大小: 344K
代理商: PC16550D
3.0
AC Electrical Characteristics
T
A
e
0
§
C to
a
70
§
C, V
DD
e a
5V
g
10%
Symbol
Parameter
Conditions
Min
Max
Units
t
ADS
t
AH
t
AR
t
AS
t
AW
t
CH
t
CS
t
CSR
t
CSW
t
DH
t
DS
t
HZ
t
MR
t
RA
t
RC
t
RCS
t
RD
t
RDD
t
RVD
t
WA
t
WC
t
WCS
t
WR
t
XH
t
XL
RC
Address Strobe Width
60
ns
Address Hold Time
0
ns
RD, RD Delay from Address
(Note 1)
30
ns
Address Setup Time
60
ns
WR, WR Delay from Address
(Note 1)
30
ns
Chip Select Hold Time
0
ns
Chip Select Setup Time
60
ns
RD, RD Delay from Chip Select
(Note 1)
30
ns
WR, WR Delay from Select
(Note 1)
30
ns
Data Hold Time
30
ns
Data Setup Time
30
ns
RD, RD to Floating Data Delay
@
100 pF loading (Note 3)
0
100
ns
Master Reset Pulse Width
5000
ns
Address Hold Time from RD, RD
(Note 1)
20
ns
Read Cycle Delay
125
ns
Chip Select Hold Time from RD, RD
(Note 1)
20
ns
RD, RD Strobe Width
125
ns
RD, RD to Driver Enable/Disable
@
100 pF loading (Note 3)
60
ns
Delay from RD, RD to Data
@
100 pF loading
60
ns
Address Hold Time from WR, WR
(Note 1)
20
ns
Write Cycle Delay
150
ns
Chip Select Hold Time from WR, WR
(Note 1)
20
ns
WR, WR Strobe Width
100
ns
Duration of Clock High Pulse
External Clock (8, Max.)
55
ns
Duration of Clock Low Pulse
External Clock (8, Max.)
55
ns
Read Cycle
e
t
AR
a
t
RD
a
t
RC
Write Cycle
e
t
AW
a
t
WR
a
t
WC
Baud Generator
280
ns
WC
280
ns
N
Baud Divisor
1
2
16
b
1
t
BHD
t
BLD
t
HW
t
LW
Receiver
Baud Output Positive Edge Delay
100 pF Load
175
ns
Baud Output Negative Edge Delay
100 pF Load
175
ns
Baud Output Up Time
f
X
e
8,
d
2, 100 pF Load
f
X
e
8,
d
2, 100 pF Load
75
ns
Baud Output Down Time
100
ns
t
RAI
Delay from Active Edge
of RD to Reset Interrupt
D
ns
t
RINT
Delay from RD, RD
(RD RBR/or RD LSR)
to Reset Interrupt
100 pF Load
1000
ns
t
RXI
Delay from RD RBR
to RXRDY Inactive
290
ns
t
SCD
t
SINT
Delay from RCLK to Sample Time
2000
ns
Delay from Stop to Set Interrupt
(Note 2)
1
RCLK
Cycles
Note 1:
Applicable only when ADS is tied low.
Note 2:
In the FIFO mode (FCR0
e
1) the trigger level interrupts, the receiver data available indication, the active RXRDY indication and the overrun error indication
will be delayed 3 RCLKs. Status indicators (PE, FE, BI) will be delayed 3 RCLKs after the first byte has been received. For subsequently received bytes these
indicators will be updated immediately after RDRBR goes inactive. Timeout interrupt is delayed 8 RCLKs.
Note 3:
Charge and discharge time is determined by V
OL
, V
OH
and the external loading.
Note 4:
These specifications are preliminary.
4
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