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参数资料
| 型号： | PC16552D |
| 厂商： | National Semiconductor Corporation |
| 英文描述： | Dual Universal Asynchronous Receiver/Transmitter with FIFOs |
| 中文描述： | 双路通用异步接收器/发射器与FIFO的 |
| 文件页数： | 16/21页 |
| 文件大小： | 291K |
| 代理商： | PC16552D |
8.0 Registers
(Continued)
TABLE III. DUART Reset Configuration
Register/Signal
Reset Control
Reset State
Interrupt Enable Register
Master Reset
0000
0000
(Note 1)
Interrupt Identification Register
Master Reset
00
00
0001
FIFO Control
Master Reset
00
00
0000
Line Control Register
Master Reset
0000
0000
MODEM Control Register
Master Reset
0000
0000
Line Status Register
Master Reset
0110
0000
MODEM Status Register
Master Reset
XXXX
0000
(Note 2)
Alternate Function Register
Master Reset
000
0 0000
SOUT
Master Reset
High
INTR (RCVR Errs)
Read LSR/MR
Low
INTR (RCVR Data Ready)
Read RBR/MR
Low
INTR (THRE)
Read IIR/Write THR/MR
Low
INTR (Modem Status Changes)
Read MSR/MR
Low
OUT 2
Master Reset
High
RTS
Master Reset
High
DTR
Master Reset
MR/FCR1
#
FCR0/
D
FCR0
MR/FCR1
#
FCR0/
D
FCR0
High
RCVR FIFO
All Bits Low
XMIT FIFO
All Bits Low
Note 1:
Boldface bits are permanently low.
Note 2:
Bits 7–4 are driven by the input signals.
8.3 PROGRAMMABLE BAUD GENERATOR
The DUART contains two independently programmable
Baud Generators. Each is capable of taking a common
clock input from DC to 24.0 MHz and dividing it by any divi-
sor from 1 to 2
16
b
1. The highest input clock frequency
recommended with a divisor
e
1 is 24 MHz. The output
frequency of the Baud Generator is 16
c
the baud rate,
[
divisor
Y
e
(frequency input)
d
(baud rate
c
16)
]
. The
output of each Baud Generator drives the transmitter and
receiver sections of the associated serial channel. Two 8-bit
latches per channel store the divisor in a 16-bit binary for-
mat. These Divisor Latches must be loaded during initializa-
tion to ensure proper operation of the Baud Generator.
Upon loading either of the Divisor Latches, a 16-bit Baud
Counter is loaded.
Table IV provides decimal divisors to use with crystal fre-
quencies of 1.8432 MHz, 3.072 MHz and 18.432 MHz. For
baud rates of 38400 and below, the error obtained is mini-
mal. The accuracy of the desired baud rate is dependent on
the crystal frequency chosen. Using a divisor of zero is
not
recommended.
8.4 LINE STATUS REGISTER
This register provides status information to the CPU con-
cerning the data transfer. Table II shows the contents of the
Line Status Register. Details on each bit follow:
Bit 0:
This bit is the receiver Data Ready (DR) indicator. Bit
0 is set to a logic 1 whenever a complete incoming charac-
ter has been received and transferred into the Receiver
Buffer Register or the FIFO. Bit 0 is reset to a logic 0 by
reading all of the data in the Receiver Buffer Register or the
FIFO.
Bit 1:
This bit is the Overrun Error (OE) indicator. Bit 1 indi-
cates that the next character received was transferred into
the Receiver Buffer Register before the CPU could read the
previously received character. This transfer destroys the
previous character. The OE indicator is set to a logic 1 dur-
ing the character stop bit time when the overrun condition
exists. It is reset whenever the CPU reads the contents of
the Line Status Register. If the FIFO mode data continues to
fill the FIFO beyond the trigger level, an overrun error will
occur only after the FIFO is full and the next character has
been completely received in the shift register. OE is indicat-
ed to the CPU as soon as it happens. The character in the
shift register can be overwritten, but it is not transferred to
the FIFO.
Bit 2:
This bit is the Parity Error (PE) indicator. Bit 2 indi-
cates that the received data character does not have the
correct even or odd parity, as selected by the even-parity-
select bit. The PE bit is set to a logic 1 during the character
Stop bit time when the character has a parity error. It is
reset to a logic 0 whenever the CPU reads the contents of
the Line Status Register or when the next character is load-
ed into the Receiver Buffer Register. In the FIFO mode this
error is associated with the particular character in the FIFO
it applies to. This error is revealed to the CPU when its
associated character is at the top of the FIFO.
Bit 3:
This bit is the Framing Error (FE) indicator. Bit 3 indi-
cates that the received character did not have a valid Stop
bit. The FE bit is set to a logic 1 when the serial channel
detects a logic 0 during the first Stop bit time. The FE indica-
tor is reset whenever the CPU reads the contents of the
Line Status Register or when the next character is loaded
into the Receiver Buffer Register. In the FIFO Mode this
error is associated with the particular character in the FIFO
it applies to. This error is revealed to the CPU when its
associated character is at the top of the FIFO. The serial
channel will try to resynchronize after a framing error. To do
this it assumes that the framing error was due to the next
start bit, so it samples this ‘‘start’’ bit twice and then takes in
the ‘‘data’’.
16
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