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参数资料
| 型号： | PC33880DWBR2 |
| 厂商： | MOTOROLA INC |
| 元件分类： | 运动控制电子 |
| 英文描述： | BRUSH DC MOTOR CONTROLLER, 2 A, PDSO28 |
| 封装： | PLASTIC, SOIC-28 |
| 文件页数： | 9/24页 |
| 文件大小： | 362K |
| 代理商： | PC33880DWBR2 |
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33880
17
Power Consumption
The 33880 device has been designed with one sleep and
one operational mode. In the sleep mode (VDD ≤2.0 V) the
current consumed by VPWR pin is less than 25 A. To place the
33880 in the sleep mode, turn all outputs off, then remove
power from VDD and the EN (enable) input pin. Prior to
removing power from the device, it is recommended all control
inputs from the micro are low. During normal operation, 4 mA
will be drawn from the VDD supply and 12 mA from the VPWR
supply.
Paralleling of Outputs
Using MOSFETS as output switches allows the connection
of any combination of outputs together. RDS(on) of MOSFETs
have an inherent positive temperature coefficient providing
balanced current sharing between outputs without destructive
operation. The device can even be operated with all outputs tied
together. This mode of operation may be desirable in the event
the application requires lower power dissipation or the added
capability of switching higher currents. Performance of parallel
operation results in a corresponding decrease in RDS(on) while
the outputs OFF open load detect currents and the output
current limits increase correspondingly (by a factor of eight if all
outputs are paralleled). Paralleling outputs from two or more
different IC devices is possible but not recommended.
Fault Logic Operation
Fault logic of the 33880 device has been greatly simplified
over other devices using SPI communications. As command
word one is being written into the shift register, a fault status
word is being simultaneously written out and received by the
MCU. Regardless of the configuration, with no outputs faulted,
all status bits being received by the MCU will be zero. When
outputs are faulted (off state open circuit or on state short
circuit/over temperature), the status bits being received by the
MCU will be one. The distinction between open circuit fault and
short/over temperature is completed via the command word.
For example, when a zero command bit is sent and a one fault
is received in the following word, the fault is open/short to
battery for high side drive or open/short to ground for low side
drive. In the same manor when a one command bit is sent and
a one fault is received in the following word the fault is a short
to ground/over temperature for high side drive or short to
battery/over temperature for low side drive. The timing between
two write words must be greater than 300 S to allow adequate
time to sense and report the proper fault status.
SPI Integrity Check
It is recommended to check the integrity of the SPI
communication with the initial power-up of the VDD and EN pins.
After initial system start-up or reset, the MCU will write one, 16
bit pattern to the 33880. The first eight bits read by the MCU will
be the fault status of the outputs while the second eight bits will
be the first byte of the bit pattern. By the MCU receiving the
same bit pattern it sent, bus integrity is confirmed. Please note
the second byte the MCU sends to the device is the command
byte and will be transferred to the outputs with rising edge of
CS.
Over Temperature Fault
Over temperature detect and shutdown circuits are
specifically incorporated for each individual output. The
shutdown following an over temperature condition is
independent of the system clock, or any other logic signal. Each
independent output shuts down at 155°C to 185°C. When an
output shuts down due to an over temperature fault, no other
outputs are affected. The MCU recognizes the fault by a one in
the fault status register. After the 33880 device has cooled
below the switch point temperature and 15°C hysteresis, the
output will activate, unless told otherwise by the MCU via SPI to
shutdown.
Over Voltage Fault
An over voltage condition on the VPWR pin will cause the
device to shutdown all outputs until the over voltage condition
is removed. When the over voltage condition is removed, the
outputs will resume their previous state. This device does not
detect an over voltage on the VDD pin. The over voltage
threshold on the VPWR pin is specified as 25 to 30 V with 1.0 V
typical hysteresis. A VPWR over voltage detect is global causing
all outputs to be turned OFF.
Output OFF Open Load Fault
An output OFF open load fault is the detection and reporting
of an
open load when the corresponding output is disabled
(input bit programmed to a logic low state). The output OFF
open load fault is detected by comparing the drain-to-source
voltage of the specific MOSFET output to an internally
generated reference. Each output has one dedicated
comparator for this purpose.
An output off open load fault is indicated when the drain-to-
source voltage is less than the output threshold voltage
(VTHRES) of 1.0 to 3.0 V. Hence, the 33880 will declare the load
open in the OFF state when the VDS is less than 1.0 V.
This device has an internal 650 A current source connected
from drain to source of the output mosfet. This prevents either
configuration of the driver from having a floating output. To
achieve low sleep mode quiescent currents, the open load
detect current source of each driver are switched off when VDD
is removed.
During output switching, especially with capacitive loads, a
false output OFF open load fault may be triggered. To prevent
this false fault from being reported, an internal fault filter of 100
to 300 S is incorporated. A false fault reporting is a function of
the load impedance, RDS(ON), COUT of the MOSFET as well as
the supply voltage, VPWR. The rising edge of CS triggers the
built-in fault delay timer. The timer will time out before the fault
comparator is enabled and the fault is detected. Once the
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