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| 型号： | PC34703PNB/R2 |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 稳压器 |
| 英文描述： | 18 A SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PQCC33 |
| 封装： | 10 X 10 MM, 2.1 MM HEIGHT, 0.8 PITCH, PLASTIC, QFN-33 |
| 文件页数： | 17/46页 |
| 文件大小： | 2509K |
| 代理商： | PC34703PNB/R2 |
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Analog Integrated Circuit Device Data
24
Freescale Semiconductor
34703
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
Figure 18. Standard Power Up/Down Sequence
in +5.0 V Supply System
Figure 19. Inverted Power Up/Down Sequence in +5.0 V
Supply System
POWER SEQUENCING
Requirements
1. I/O supply voltage not to exceed core voltage by more
than 2.5 V.
2. Core supply voltage not to exceed I/O voltage by more
than 0.4 V.
Methods of Control
The 34703 has several methods of monitoring and
controlling the regulator output voltages, as described in the
paragraphs below. Power sequencing control is also
achieved through the intrinsic operation of the regulators.
The EN1 and EN2 terminals can be used to disable the power
Intrinsic Operation
For both the LDO and switcher, whenever the output
voltage is below the regulation point, the LDO external Pass
FET will be on or the Buck High-Side FET will be on at a duty
cycle controlled by the switcher. Because these devices are
FETs, current can flow in either direction, balancing the
voltages via the common supply terminal. The ability to
maintain the FETs on will depend on the available gate
voltage, and thus the size of the boost regulator storage
capacitor.
Standard Power Sequencing Control
Comparators monitor voltage differences between the
LDO (LDO terminal) and the switcher (VOUT terminal) outputs
as follows:
1. LDO > VOUT + 2.3 V, turn off LDO. The LDO can be
forced off. This occurs whenever the LDO output
voltage exceeds the switcher output voltage by more
than 2.3 V.
2. LDO > VOUT + 2.4 V, shunt LDO to ground. If turning
off the LDO is insufficient and the LDO output voltage
exceeds the switcher output voltage by more than
2.4 V, a 1.0 shunt FET is turned on that discharges
the LDO load capacitor to ground. The shunt FET is
used for switcher output shorts to ground and for power
down in case of VIN1 ≠ VIN2 with the switcher output
falling faster than the LDO.
3. LDO < VOUT + 2.2 V, cancel (1) and (2) above, re-
enable LDO. Normal operation resumes when the LDO
output voltage is less than 2.2 V above the switcher
output voltage.
4. LDO < VOUT - 0.1 V, turn off switcher. The switcher can
be forced off. This occurs whenever the LDO is less
than VOUT - 0.1 V.
5. LDO < VOUT - 0.3 V, turn on Sync (LS) FET and 1.0
VOUT sink FET. The Buck High-Side FET is forced off
and the Sync FET is forced on. This occurs when the
V = 2.5 V
Max. Lead
V = 0.4 V
Max. Lag
V = 0.4 V
Max. Lag
V Start-Up
3.3 V I/O Voltage (VLDO)
1.8 V Core Voltage
(VOUT)
5.0 V Input Supply
V = 2.5 V
Max. Lead
34703
5.0 Vinput
VDDH (I/O)
VDDL (Core)
MCU
POR
VIN1
LDRV
LDO
LFB
ISNS
RESET
SW_A
PGND
INV
CLKSEL
GND
BOOT
VOUT
LCMP
ADDR
VDDI
CLKSYN
FREQ
EN1
SDA
SCL
EN2
VBD
VBST (sense)
VIN2
VBST
SR
SW_B
VBST
COMP
RT
3.3 V
1.5 V
5.0 V
Optional
V = 2.5 V
Max. Lead
V = 0.4 V
Max. Lag
V = 0.4 V
Max. Lag
V Start-Up
3.3 V I/O Voltage (VOUT)
1.8 V Core Voltage(VLDO)
5.0 V Input Supply
V = 2.5 V
Max. Lead
34703
5.0 Vinput
VDDL (Core)
VDDH (I/O)
MCU
POR
VIN1
LDRV
LDO
LFB
ISNS
RESET
SW_A
PGND
INV
CLKSEL
GND
BOOT
VOUT
LCMP
ADDR
VDDI
CLKSYN
FREQ
EN1
SDA
SCL
EN2
VBD
VBST (sense)
VIN2
VBST
SR
SW_B
VBST
COMP
RT
3.3 V
1.5 V
5.0 V
Optional
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