Analog Integrated Circuit Device Data
Freescale Semiconductor
17
34703
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 34703 power supply integrated circuit provides the
means to efficiently supply the Power QUICC and other
families of Freescale microprocessors. It incorporates a high-
performance synchronous buck regulator, supplying the
microprocessor’s core, and a low dropout (LDO) linear
regulator providing the microprocessor I/O and bus voltages.
This device incorporates many advanced features; e.g.,
precisely maintained up/down power sequencing, ensuring
the proper operation and protection of the CPU and power
system. At the same time, it provides high flexibility of
configuration, allowing the maximum optimization of the
power supply system.
FUNCTIONAL TERMINAL DESCRIPTION
BOOST VOLTAGE TERMINAL (VBST)
Internal boost regulator output voltage. The internal boost
regulator provides a 45 mA output current to supply the drive
circuits for the integrated power MOSFETs and the external
N-channel power MOSFET of the linear regulator. The
voltage at the VBST terminal is 8.0 V nominal.
ENABLE 1 AND 2 TERMINALS (EN1 AND EN2)
These two terminals permit positive logic control of the
Enable function and selection of the Power Sequencing
mode concurrently.
Table 5 depicts the EN1 and EN2
function and Power Sequencing mode selection.
Both EN1 and EN2 terminals have internal pulldown
resistors and both can withstand a short circuit to the supply
voltage, 13.5 V.
CLOCK SELECTION TERMINAL (CLKSEL)
This terminal sets the CLKSYN terminal as either an
oscillator output or a synchronization input terminal. The
CLKSEL terminal is also used for the I2C address selection.
INPUT VOLTAGE 1 TERMINAL (VIN1)
The input supply terminal for the integrated circuit. The
internal circuits of the IC are supplied through this terminal.
SERIAL CLOCK TERMINAL (SCL)
I2C bus terminal. Serial clock.
OSCILLATOR FREQUENCY TERMINAL (FREQ)
This switcher frequency selection terminal can be adjusted
by connecting external resistor RF to the FREQ terminal. The
default switching frequency (FREQ terminal left open or tied
to VDDI) is set to 300 kHz.
ADDRESS TERMINAL (ADDR)
The ADDR terminal is used to set the address of the
device when used in an I2C communication. This terminal
can either be tied to VDDI or grounded through a 10 k
information on this terminal.
RESET OUTPUT TERMINAL (RESET)
The Reset Control circuit monitors both the switching
regulator and the LDO feedback voltages. It is an open drain
output and has to be pulled up to some supply voltage (e.g.,
the output of the LDO) by an external resistor.
The Reset Control circuit supervises both output
voltages—the linear regulator output VLDO and the switching
regulator output VOUT. When either of these two regulators
is out of regulation (high or low), the RST terminal is pulled
low. There is a 20 s delay filter preventing erroneous resets.
During power-up sequencing, RST is held low until the Reset
Timer times out.
LINEAR COMPENSATION TERMINAL (LCMP)
Linear regulator compensation terminal.
CURRENT SENSE TERMINAL (ISNS)
Current sense terminal of the LDO. Overcurrent protection
of the linear regulator external power MOSFET. The voltage
drop over the LDO current sense resistor RS is sensed
between the ISNS and LDO terminals. The LDO current limit
can be adjusted by selecting the proper value of the current
sensing resistor RS.
LINEAR REGULATOR TERMINAL (LDO)
Input terminal of the linear regulator power sequence
control circuit.
Table 5. Operating Mode Selection
EN1
EN2
Operating Mode
0
Regulators Disabled
0
1
Standard Power Sequencing
1
0
Inverted Power Sequencing
1
No Power Sequencing,
Regulators Enabled