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参数资料
| 型号： | PC66-222-620 |
| 厂商： | SIEMENS AG |
| 英文描述： | 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module |
| 中文描述： | 3.3 4米× 64/72-Bit一银行内存模块3.3 8米× 64/72-Bit 2银行内存模块 |
| 文件页数： | 10/15页 |
| 文件大小： | 76K |
| 代理商： | PC66-222-620 |
HYS64(72)V4200/8220GU
SDRAM-Modules
Semiconductor Group
10
Notes:
1. These parameters depend on the cycle rate. These values are measured at 100 MHz for -8 and
-8B and at 66 MHz for -10 modules. Input signals are changed once during tck, excepts for ICC6
and for standby currents when tck=infinity. All values are shown per memory component.
2. These parameters are measured with continous data stream during read access and all DQ
toggling. CL=3 and BL=4 assumed and the VDDQ current is excluded.
3. All AC characteristics are shown for device level.
An initial pause of 100
μ
s is required after power-up, then a Precharge All Banks command must
be given followed by 8 Auto Refresh (CBR) cycles before the Mode Register Set Operation can
begin.
4. AC timing tests have V
il
= 0.4 V and V
ih
= 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between V
ih
and V
il
. All AC measurements assume t
T
=1ns
with the AC output load circuit show. Specified tac and toh parameters are measured with a 50
pF only, without any resistive termination and with a input signal of 1V / ns edge rate between
0.8V and 2.0 V.
tCH
5. If clock rising time is longer than 1ns, a time (t
T
/2 -0.5) ns has to be added to this parameter.
6. Rated at 1.5 V
7. If t
T
is longen than 1 ns, a time (t
T
-1) ns has to be added to this parameter.
8. Any time that the refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh
commands must be given to “wake-up“ the device.
9. Self Refresh Exit is a synchronous operation and begins on the 2nd positive clock edge after
CKE returns high. Self Refresh Exit is not complete until a time period equal to tRC is satisfied
once the Self Refresh Exit command is registered.
10.Referenced to the time which the output achieves the open circuit condition, not to output voltage
levels.
1.4V
1.4V
tSETUP
tHOLD
tAC
tAC
tLZ
tOH
tHZ
CLOCK
INPUT
OUTPUT
50 pF
I/O
Z=50 Ohm
+ 1.4 V
50 Ohm
2.4 V
0.4 V
t
T
fig.1
tCL
50 pF
I/O
Measurement conditions for
tac and toh
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