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参数资料
| 型号： | PC66-222-620 |
| 厂商： | SIEMENS AG |
| 英文描述： | 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module |
| 中文描述： | 3.3 4米× 64/72-Bit一银行内存模块3.3 8米× 64/72-Bit 2银行内存模块 |
| 文件页数： | 11/15页 |
| 文件大小： | 76K |
| 代理商： | PC66-222-620 |
HYS64(72)V4200/8220GU
SDRAM-Modules
Semiconductor Group
11
A serial presence detect storage device - E
2
PROM - is assembled onto the module. Information about the module
configuration, speed, etc. is written into the E
2
PROM device during module production using a serial presence
detect protocol ( I
2
C synchronous 2-wire bus)
SPD-Table for PC100 modules:
Byte#
Description
SPD Entry
Value
Hex
4Mx64
-8
80
08
04
0C
4Mx64
-8B
80
08
04
0C
4Mx72
-8
80
08
04
0C
8Mx64
-8
80
08
04
0C
8Mx64
-8B
80
08
04
0C
8Mx72
-8
80
08
04
0C
0
1
2
3
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (wit-
hout BS bits)
Number of Column Addresses
(for 16 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock
at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
12
4
8
08
08
08
08
08
08
5
6
7
8
9
1 / 2
64
0
LVTTL
10.0 ns
6.0 ns
01
40
00
01
A0
60
01
40
00
01
A0
60
01
48
00
01
A0
60
02
40
00
01
A0
60
02
40
00
01
A0
60
02
48
00
01
A0
60
10
11
12
none
00
80
00
80
02
80
00
80
00
80
02
80
Self-Refresh,
15.6
μ
s
x16
n/a / x8
13
14
SDRAM width, Primary
Error Checking SDRAM data
width
Minimum clock delay for back-to-
back random column address
Burst Length supported
10
00
10
00
10
08
10
00
10
00
10
08
15
t
ccd
= 1 CLK
01
01
01
01
01
01
16
1, 2, 4, 8 & full
page
4
CL = 2 & 3
CS latency = 0
WL = 0
non buffered/
non reg.
Vcc tol +/- 10%
8F
8F
8F
8F
8F
8F
17
18
19
20
21
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
22
SDRAM Device Attributes :Gene-
ral
Minimum Clock Cycle Time at
CAS Latency = 2
Maximum data access time from
Clock for CL=2
Minimum Clock Cycle Time at CL
= 1
Maximum Data Access Time
from Clock at CL=1
Minimum Row Precharge Time
06
06
06
06
06
06
23
10.0 / 12.0ns
A0
C0
A0
A0
C0
A0
24
6.0 / 7.0ns
60
70
60
60
70
60
25
not supported
FF
FF
FF
FF
FF
FF
26
not supported
FF
FF
FF
FF
FF
FF
27
20 / 30 ns
14
1E
14
14
1E
14
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