参数资料
型号: PC66-222-620
厂商: SIEMENS AG
英文描述: 3.3V 4M x 64/72-Bit 1 BANK SDRAM Module 3.3V 8M x 64/72-Bit 2 BANK SDRAM Module
中文描述: 3.3 4米× 64/72-Bit一银行内存模块3.3 8米× 64/72-Bit 2银行内存模块
文件页数: 13/15页
文件大小: 76K
代理商: PC66-222-620
HYS64(72)V4200/8220GU
SDRAM-Modules
Semiconductor Group
13
SPD-Table for PC66 modules:
Byte#
Description
SPD Entry
Value
Hex
4Mx64
-10
80
08
04
0C
08
4Mx72
-10
80
08
04
0C
08
8Mx64
-10
80
08
04
0C
08
8Mx72
-10
80
08
04
0C
08
0
1
2
3
4
Number of SPD bytes
Total bytes in Serial PD
Memory Type
Number of Row Addresses (without BS bits)
Number of Column Addresses
(for x16 SDRAM)
Number of DIMM Banks
Module Data Width
Module Data Width (cont’d)
Module Interface Levels
SDRAM Cycle Time at CL=3
SDRAM Access time from Clock at CL=3
Dimm Config (Error Det/Corr.)
Refresh Rate/Type
128
256
SDRAM
12
8
5
6
7
8
9
1 / 2
64
0
LVTTL
10.0 ns
7.0 ns
none
Self-Refresh,
15.6
μ
s
x16
n/a / x8
t
ccd
= 1 CLK
01
40
00
01
A0
70
00
80
01
48
00
01
A0
70
02
80
02
40
00
01
A0
70
00
80
02
48
00
01
A0
70
02
80
10
11
12
13
14
15
SDRAM width, Primary
Error Checking SDRAM data width
Minimum clock delay for back-to-back ran-
dom column address
Burst Length supported
10
00
01
10
08
01
10
00
01
10
08
01
16
1, 2, 4, 8 & full
page
4
CL = 2 & 3
CS latency = 0
WL = 0
non buffered/
non reg.
Vcc tol +/- 10%
15.0 ns
8F
8F
8F
8F
17
18
19
20
21
Number of SDRAM banks
Supported CAS Latencies
CS Latencies
WE Latencies
SDRAM DIMM module attributes
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
04
06
01
01
00
22
23
SDRAM Device Attributes :General
Minimum Clock Cycle Time at CAS Latency
= 2
Maximum data access time from Clock for
CL=2
Minimum Clock Cycle Time at CL = 1
Maximum Data Access Time from Clock at
CL=1
Minimum Row Precharge Time
Minimum Row Active to Row Active delay
tRRD
06
F0
06
F0
06
F0
06
F0
24
8.0 ns
80
80
80
80
25
26
not supported
not supported
FF
FF
FF
FF
FF
FF
FF
FF
27
28
24 ns
20 ns
18
14
18
14
18
14
18
14
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