参数资料
型号: PCA85176H/Q900/1,5
厂商: NXP Semiconductors
文件页数: 22/59页
文件大小: 0K
描述: IC LCD DRIVER 40SEG 64TQFP
产品培训模块: I²C Bus Fundamentals
标准包装: 1
显示器类型: LCD
配置: 40 段
接口: I²C
电流 - 电源: 80µA
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 95°C
安装类型: 表面贴装
封装/外壳: 64-TQFP
供应商设备封装: 64-TQFP(10x10)
包装: 标准包装
其它名称: 568-5108-6
NXP Semiconductors
PCA85176
Automotive LCD driver for low multiplex rates
7.6 Display RAM
The display RAM is a static 40 ? 4-bit RAM which stores LCD data.
There is a one-to-one correspondence between
? the bits in the RAM bitmap and the LCD elements
? the RAM columns and the segment outputs
? the RAM rows and the backplane outputs.
A logic 1 in the RAM bitmap indicates the on-state of the corresponding LCD element;
similarly, a logic 0 indicates the off-state.
The display RAM bitmap, Figure 12 , shows the rows 0 to 3 which correspond with the
backplane outputs BP0 to BP3, and the columns 0 to 39 which correspond with the
segment outputs S0 to S39. In multiplexed LCD applications the segment data of the first,
second, third, and fourth row of the display RAM are time-multiplexed with BP0, BP1,
BP2, and BP3 respectively.
display RAM addresses (columns)/segment outputs (S)
0
1
2
3
4
35
36
37
38
39
0
display RAM bits
(rows)/
backplane outputs
(BP)
1
2
3
mbe525
The display RAM bitmap shows the direct relationship between the display RAM column and the
segment outputs; and between the bits in a RAM row and the backplane outputs.
Fig 12. Display RAM bitmap
When display data is transmitted to the PCA85176, the display bytes received are stored
in the display RAM in accordance with the selected LCD drive mode. The data is stored as
it arrives and depending on the current multiplex drive mode the bits are stored singularly,
in pairs, triples, or quadruples. To illustrate the filling order, an example of a 7-segment
display showing all drive modes is given in Figure 13 ; the RAM filling organization
depicted applies equally to other LCD types.
? In static drive mode the eight transmitted data bits are placed into row 0 as one byte
? In 1:2 multiplex drive mode the eight transmitted data bits are placed in pairs into
row 0 and 1 as two successive 4-bit RAM words
? In 1:3 multiplex drive mode the eight bits are placed in triples into row 0, 1, and 2 as
three successive 3-bit RAM words, with bit 3 of the third address left unchanged. It is
not recommended to use this bit in a display because of the difficult addressing. This
last bit may, if necessary, be controlled by an additional transfer to this address, but
care should be taken to avoid overwriting adjacent data because always full bytes are
transmitted (see Section 7.6.3 )
? In 1:4 multiplex drive mode, the eight transmitted data bits are placed in quadruples
into row 0, 1, 2, and 3 as two successive 4-bit RAM words
PCA85176
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 11 July 2013
? NXP B.V. 2013. All rights reserved.
22 of 59
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