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| 型号： | PCA9502BS,151 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 7/25页 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C/SPI 24HVQFN |
| 产品培训模块： | I²C Bus Fundamentals |
| 特色产品： | NXP - I2C Interface |
| 标准包装： | 490 |
| 接口： | I²C，SPI |
| 输入/输出数： | 8 |
| 中断输出： | 无 |
| 频率 - 时钟： | 400kHz |
| 电源电压： | 2.3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 供应商设备封装： | 24-HVQFN（4x4） |
| 包装： | 托盘 |
| 产品目录页面： | 824 (CN2011-ZH PDF) |
| 其它名称： | 568-3635 935281363151 PCA9502BS-S |
PCA9502_3
NXP B.V. 2006. All rights reserved.
Product data sheet
Rev. 03 — 13 October 2006
15 of 25
NXP Semiconductors
PCA9502
8-bit I/O expander with I2C-bus/SPI interface
[1]
5.5 V steady state voltage tolerance on inputs and outputs is valid only when the supply voltage is present. 3.8 V steady state voltage
tolerance on inputs and outputs when no supply voltage is present.
13. Dynamic characteristics
[1]
A detailed description of the I2C-bus specication, with applications, is given in brochure
“The I2C-bus and how to use it”. This brochure
may be ordered using the code 9398 393 40011.
[2]
Minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if SDA is held LOW for a
minimum of 25 ms.
I2C-bus inputs SCL, CS/A0, SI/A1
VIH
HIGH-level input voltage
1.6
5.5[1]
2.0
5.5[1]
V
VIL
LOW-level input voltage
-
0.6
-
0.8
V
IL
leakage current
-10-10
A
Ci
input capacitance
-7-7
pF
Table 15.
Static characteristics …continued
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = 40 °Cto+85 °C; unless otherwise specied.
Symbol
Parameter
Conditions
VDD = 2.5 V
VDD = 3.3 V
Unit
Min
Max
Min
Max
Table 16.
I2C-bus timing specications
All the timing limits are valid within the operating supply voltage, ambient temperature range and output load;
VDD = (2.5 V ± 0.2 V) or (3.3 V ± 0.3 V); Tamb = 40 °Cto+85 °C; refer to VIL and VIH with an input voltage of VSS to VDD.
All output load = 25 pF, except SDA output load = 400 pF.[1]
Symbol Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Unit
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
kHz
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
s
tHD;STA
hold time (repeated) START condition
4.0
-
0.6
-
s
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
s
tSU;STO
set-up time for STOP condition
4.7
-
0.6
-
s
tHD;DAT
data hold time
0
-
0
-
ns
tVD;ACK
data valid acknowledge time
-
0.6
-
0.6
s
tVD;DAT
data valid time
SCL LOW to data out valid
-
0.6
-
0.6
ns
tSU;DAT
data set-up time
250
-
150
-
ns
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
s
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
s
tf
fall time of both SDA and SCL signals
-
300
-
300
ns
tr
rise time of both SDA and SCL signals
-
1000
-
300
ns
tSP
pulse width of spikes that must be
suppressed by the input lter
-
50
-
50
ns
td1
I2C-bus GPIO output valid time
0.5
-
0.5
-
s
td4
I2C input pin interrupt valid time
0.2
-
0.2
-
s
td5
I2C input pin interrupt clear time
0.2
-
0.2
-
s
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