参数资料
型号: PCA9505DGG,112
厂商: NXP Semiconductors
文件页数: 2/34页
文件大小: 0K
描述: IC I/O EXPANDER I2C 40B 56TSSOP
产品培训模块: I²C Bus Fundamentals
特色产品: NXP - I2C Interface
标准包装: 35
接口: I²C
输入/输出数: 40
中断输出:
频率 - 时钟: 400kHz
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 56-TFSOP(0.240",6.10mm 宽)
供应商设备封装: 56-TSSOP
包装: 管件
包括: POR
产品目录页面: 824 (CN2011-ZH PDF)
其它名称: 568-4244-5
935284486112
PCA9505DGG
PCA9505_9506
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 4 — 3 August 2010
10 of 34
NXP Semiconductors
PCA9505/06
40-bit I2C-bus I/O port with RESET, OE and INT
7.3.1 IP0 to IP4 - Input Port registers
These registers are read-only. They reflect the incoming logic levels of the port pins
regardless of whether the pin is defined as an input or an output by the I/O Configuration
register. If the corresponding Px[y] bit in the PI registers is set to logic 0, or the inverted
incoming logic levels if the corresponding Px[y] bit in the PI register is set to logic 1. Writes
to these registers have no effect.
The Polarity Inversion register can invert the logic states of the port pins. The polarity of
the corresponding bit is inverted when Px[y] bit in the PI register is set to logic 1. The
polarity of the corresponding bit is not inverted when Px[y] bits in the PI register is set to
logic 0.
Mask Interrupt registers
20
100000
MSK0
read/write
Mask Interrupt register bank 0
21
100001
MSK1
read/write
Mask Interrupt register bank 1
22
100010
MSK2
read/write
Mask Interrupt register bank 2
23
100011
MSK3
read/write
Mask Interrupt register bank 3
24
100100
MSK4
read/write
Mask Interrupt register bank 4
25
100101
-
reserved for future use
26
100110
-
reserved for future use
27
100111
-
reserved for future use
Table 3.
Register summary …continued
Register #
(hex)
D5
D4
D3
D2
D1
D0
Symbol
Access
Description
Table 4.
IP0 to IP4 - Input Port registers (address 00h to 04h) bit description
Legend: * default value ‘X’ determined by the externally applied logic level.
Address
Register
Bit
Symbol
Access
Value
Description
00h
IP0
7 to 0
I0[7:0]
R
XXXX XXXX*
Input Port register bank 0
01h
IP1
7 to 0
I1[7:0]
R
XXXX XXXX*
Input Port register bank 1
02h
IP2
7 to 0
I2[7:0]
R
XXXX XXXX*
Input Port register bank 2
03h
IP3
7 to 0
I3[7:0]
R
XXXX XXXX*
Input Port register bank 3
04h
IP4
7 to 0
I4[7:0]
R
XXXX XXXX*
Input Port register bank 4
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