参数资料
型号: PCA9534APWR
厂商: TEXAS INSTRUMENTS INC
元件分类: 微控制器/微处理器
英文描述: 8 I/O, PIA-GENERAL PURPOSE, PDSO16
封装: GREEN, PLASTIC, TSSOP-16
文件页数: 34/41页
文件大小: 985K
代理商: PCA9534APWR
14
I/O
Port
Shift
Register
8 Bits
LP Filter
Interrupt
Logic
Input
Filter
15
Power-On
Reset
Read Pulse
Write Pulse
2
1
13
16
8
GND
VCC
SDA
SCL
A1
A0
INT
I2C Bus
Control
P7P0
3
A2
SCPS141F – SEPTEMBER 2006 – REVISED JUNE 2010
www.ti.com
Table 2. TERMINAL FUNCTIONS
NO.
QSOP (DBQ),
SOIC (DW),
QFN (RGT)
NAME
DESCRIPTION
SSOP (DB),
AND
TSSOP (PW), AND
QFN (RGV)
TVSOP (DGV)
1
15
A0
Address input. Connect directly to VCC or ground.
2
16
A1
Address input. Connect directly to VCC or ground.
3
1
A2
Address input. Connect directly to VCC or ground.
4
2
P0
P-port input/output. Push-pull design structure.
5
3
P1
P-port input/output. Push-pull design structure.
6
4
P2
P-port input/output. Push-pull design structure.
7
5
P3
P-port input/output. Push-pull design structure.
8
6
GND
Ground
9
7
P4
P-port input/output. Push-pull design structure.
10
8
P5
P-port input/output. Push-pull design structure.
11
9
P6
P-port input/output. Push-pull design structure.
12
10
P7
P-port input/output. Push-pull design structure.
13
11
INT
Interrupt output. Connect to VCC through a pullup resistor.
14
12
SCL
Serial clock bus. Connect to VCC through a pullup resistor.
15
13
SDA
Serial data bus. Connect to VCC through a pullup resistor.
16
14
VCC
Supply voltage
LOGIC DIAGRAM (POSITIVE LOGIC)
A.
Pin numbers shown are for DB, DBQ, DGV, DW, or PW package.
B.
All I/Os are set to inputs at reset.
4
Copyright 2006–2010, Texas Instruments Incorporated
Product Folder Link(s): PCA9534A
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