参数资料
| 型号： | PCA9535EMTTXG |
| 厂商： | ON Semiconductor |
| 文件页数： | 4/20页 |
| 文件大小： | 0K |
| 描述： | 16-BIT I/O EXPANDER |
| 标准包装： | 3,000 |
| 接口： | I²C 总线，SM 总线 |
| 输入/输出数： | 16 |
| 中断输出： | 是 |
| 频率 - 时钟： | 100kHz |
| 电源电压： | 1.65 V ~ 5.5 V |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘 |
| 供应商设备封装： | 24-QFN（4x4） |
| 包装： | 带卷 (TR) |
| 包括： | * |
PCA9535E, PCA9535EC
http://onsemi.com
12
Figure 8. Read from Register
Remark: Transfer can be stopped at any time by a STOP condition.
A
S
START condition
R/W
acknowledge
from slave
A
acknowledge
from slave
SDA
AP
acknowledge
from master
DATA (first byte)
slave address
STOP
condition
S
(repeated)
START condition
(cont.)
A2 A1 A0 1A
A6
R/W
acknowledge
from slave
slave address
at this moment mastertransmitter becomes masterreceiver
and slavereceiver becomes slavetransmitter
NA
no acknowledge
from master
COMMAND BYTE
A2 A1 A0
A6
0
data from lower or
upper byte of register
LSB
MSB
DATA (last byte)
data from upper or
lower byte of register
LSB
MSB
A5 A4 A3
Figure 9. Read from Input Port Register, Scenario 1
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
A2 A1 A0 1 A
S A6
START condition
R/W
acknowledge
from slave
A
SCL
SDA
A
read from port 0
P
9
8
7
6
5
4
3
2
1
I0.x
slave address
7
STOP condition
acknowledge
from master
A
I1.x
7
acknowledge
from master
A
I0.x
7
acknowledge
from master
1
I1.x
7
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
t v(INT_N)
trst(INT_N)
A5 A4 A3
654 32 1 0
65 4 3 2 1 0
654 32 1 0
Figure 10. Read from Input Port Register, Scenario 2
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge
phase is valid (output mode). It is assumed that the command byte has previously been set to ’00’ (read Input Port register).
A2 A1 A0 1 A
S A6
START condition
R/W
acknowledge
from slave
A
SCL
SDA
A
read from port 0
P
9
8
7
6
5
4
3
2
1
I0.x
slave address
STOP condition
acknowledge
from master
A
I1.x
acknowledge
from master
A
I0.x
acknowledge
from master
1
I1.x
non acknowledge
from master
data into port 0
read from port 1
data into port 1
INT
tv(INT_N)
t rst(INT_N)
2
1
A
T
A
D
3
0
A
T
A
D
0
1
A
T
A
D
0
A
T
A
D
DATA 00
DATA 01
th(D)
DATA 02
tsu(D)
DATA 03
tsu(D)
2
1
A
T
A
D
1
A
T
A
D
0
1
A
T
A
D
A5A4 A3
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