参数资料
型号: PCA9672D,512
厂商: NXP Semiconductors
文件页数: 13/36页
文件大小: 0K
描述: IC I/O EXPANDER I2C 8B 16SOIC
标准包装: 48
接口: I²C
输入/输出数: 8
中断输出:
频率 - 时钟: 1MHz
电源电压: 2.3 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SO
包装: 管件
包括: POR
其它名称: 935282746512
PCA9672D
PCA9672D-ND
PCA9672
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 27 May 2013
20 of 36
NXP Semiconductors
PCA9672
Remote 8-bit I/O expander for Fm+ I2C-bus with interrupt and reset
[1]
The power-on reset circuit resets the I2C-bus logic with VDD <VPOR and set all I/Os to logic 1 (with current source to VDD).
[2]
Each bit must be limited to a maximum of 25 mA and the total package limited to 200 mA due to internal busing limits.
[3]
The value is not tested, but verified on sampling basis.
14. Dynamic characteristics
Inputs AD0, AD1
VIL
LOW-level input voltage
0.5
-
+0.3VDD
V
VIH
HIGH-level input voltage
0.7VDD
-5.5
V
ILI
input leakage current
1-
+1
A
Ci
input capacitance
-
3
5
pF
Table 8.
Static characteristics …continued
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 9.
Dynamic characteristics
VDD = 2.3 V to 5.5 V; VSS =0V; Tamb = 40 Cto+85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Standard mode
I2C-bus
Fast mode I2C-bus
Fast mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
fSCL
SCL clock frequency
0
100
0
400
0
1000
kHz
tBUF
bus free time between a
STOP and START
condition
4.7
-
1.3
-
0.5
-
s
tHD;STA
hold time (repeated)
START condition
4.0
-
0.6
-
0.26
-
s
tSU;STA
set-up time for a repeated
START condition
4.7
-
0.6
-
0.26
-
s
tSU;STO
set-up time for STOP
condition
4.0
-
0.6
-
0.26
-
s
tHD;DAT
data hold time
0
-
0
-
0
-
ns
tVD;ACK
data valid acknowledge
time
0.3
3.45
0.1
0.9
0.05
0.45
s
tVD;DAT
data valid time
300
-
50
-
50
450
ns
tSU;DAT
data set-up time
250
-
100
-
50
-
ns
tLOW
LOW period of the SCL
clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of the SCL
clock
4.0
-
0.6
-
0.26
-
s
tf
fall time of both SDA and
SCL signals
-300
20 + 0.1Cb[3]
300
-
120
ns
tr
rise time of both SDA and
SCL signals
-
1000
20 + 0.1Cb[3]
300
-
120
ns
tSP
pulse width of spikes that
must be suppressed by the
input filter
-50
-
50
-
50
ns
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