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参数资料
| 型号： | PCF8598C-2T/02,118 |
| 厂商： | NXP Semiconductors |
| 文件页数： | 7/21页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT 100KHZ 8SOIC |
| 标准包装： | 1,000 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K (1K x 8) |
| 速度： | 100kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 6.0 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 8-SO |
| 包装： | 带卷 (TR) |
| 其它名称： | 935182390118 PCF8598C2D-T PCF8598C2D-T-ND |
Philips Semiconductors
PCF8598C-2
1024 × 8-bit CMOS EEPROM with I 2 C-bus interface
The master receiver must generate an acknowledge after the reception of each byte
that has been clocked out of the slave transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge
clock pulse in such a way that the SDA line is stable LOW during the HIGH period of
the acknowledge related clock pulse.
Set-up and hold times must be taken into account. A master receiver must signal an
end of data to the slave transmitter by not generating an acknowledge on the last byte
that has been clocked out of the slave. In this event, the transmitter must leave the
data line HIGH to enable the master generation of the STOP condition.
8.1.3
Device addressing
Following a START condition, the bus master must output the address of the slave it
is accessing. The address of the PCF8598C-2 is shown in Figure 4 . To conserve
power, no internal pull-up resistors are incorporated on the hardware selectable pins
and they must be connected to either V DD or V SS .
1
0
1
0
A2
A1
A0 R/W
FIXED
SOFTWARE
SELECTABLE
HARDWARE
SELECTABLE
002aaa257
Fig 4. Slave address.
The last bit of the slave address de?nes the operation to be performed. When set to
logic 1, a read operation is selected, while a logic 0 selects a write operation.
9397 750 14219
8.1.4
Write operations
A write-protection input at Pin 1 (WP) allows disabling of write commands from the
master by a hardware signal. Write accesses are allowed to either the upper or lower
512 bytes of the EEPROM if the pin WP is LOW or the lower 512 bytes of the
EEPROM if the pin WP is HIGH. When the pin WP is HIGH the upper 512 bytes of
the EEPROM are write-protected and no acknowledge will be given by the
PCF8598C-2 when data is sent. However, an acknowledge will be given after the
slave address and the word address.
Byte/word write: For a write operation, the PCF8598C-2 requires a second address
?eld. This address ?eld is a word address providing access to the 256 words of
memory. Upon receipt of the word address, the PCF8598C-2 responds with an
acknowledge and awaits the next eight bits of data, again responding with an
acknowledge. Word address is automatically incremented. The master can now
terminate the transfer by generating a STOP condition or transmit up to six more
bytes of data and then terminate by generating a STOP condition.
After this STOP condition, the E/W cycle starts and the bus is free for another
transmission. Its duration is 10 ms per byte.
During the E/W cycle the slave receiver does not send an acknowledge bit if
addressed via the I 2 C-bus.
? Koninklijke Philips Electronics N.V. 2004. All rights reserved.
Product data
Rev. 06 — 22 October 2004
7 of 21
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