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SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM
Within 6/fS
t(DACDLY2)
(32/fS)
Normal Data
VCOM
(0.5 VCC2)
Undefined
Data
Normal Data
Synchronous
Asynchronous
Synchronous
Resynchronization
Synchronization Lost
DAC VOUT
State of Synchronization
Normal Data
Zero Data
Normal Data
ADC DOUT
t(ADCDLY2)
(32/fS)
Undefined
Data
T0020-07
Normal Data
Low
Normal Data
DOUTS
Undefined
Data
MICROPHONE AMPLIFIER AND MICROPHONE BIAS GENERATOR
PCM3052A
SLES160 – NOVEMBER 2005
The PCM3052A operates with LRCK and BCK synchronized to the system clock in slave mode. The PCM3052A
does not need specific phase relationship among LRCK, BCK, and the system clock, but does require the
synchronization of LRCK, BCK, and the system clock.
If the relationship between system clock and LRCK changes more than
±6 BCKs during one sample period due
to LRCK jitter, etc., internal operation of DAC halts within 6/fS, and the analog output is forced to 0.5 VCC2 until
re-synchronization of the system clock to LRCK and BCK has completed and then the time of t(DACDLY2) has
elapsed.
DOUTS is also held LOW during the same period.
Internal operation of the ADC also halts within 6/fS, and digital output is forced into ZERO code until
re-synchronization of the system clock to LRCK and BCK has completed and then the time of t(ADCDLY2) has
elapsed.
In case of changes less than
±5 BCKs, re-synchronization does not occur and the previously described
analog/digital output control and discontinuity does not occur.
Figure 48 illustrates the DAC analog output, ADC digital output, and DOUTS output for loss of synchronization.
During undefined data, the PCM3052A can generate some noise in audio signal. Also, the transition of normal to
undefined data and undefined or zero data to normal creates a discontinuity of data on analog and digital
outputs, which could generate some noise in audio signal.
Figure 48. DAC Output and ADC Output for Loss of Synchronization
The PCM3052A has a built-in, high-performance differential-input microphone amplifier with 34-dB gain, 5-k
(minimum) input resistance, and 59-dB SNR at 100-mVrms output. Bandwidth is 20 kHz for –3-dB attenuation.
The PCM3052A also has a low-noise microphone bias generator with 0.75-VCC1 and 1-mA current-source
capability for electret microphones. Output impedance is 48
for external noise reduction. The output of the
microphone amplifier and the line input are connected as inputs to the multiplexer. The serial control port can be
used to control which input the multiplexer selects (see
Figure 50).
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