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DESIGN AND LAYOUT CONSIDERATIONS IN APPLICATION
Power Supply Pins (VCC1, VCC2, VCC3, VDD)
Grounding (AGND1, AGND2, AGND3, DGND)
VINL, VINR Pins
VREF1, VREF2, VCOM Pins
MBIAS Pin
REFO Pin
MINM, MINP Pins
System Clock
External Mute Control
PCM3052A
SLES160 – NOVEMBER 2005
The digital and analog power supply lines to the PCM3052A should be bypassed to the corresponding ground
pins with 0.1-
F ceramic and 10-F electrolytic capacitors as close to the pins as possible to maximize the
dynamic performance of the ADC and DAC.
Although the PCM3052A has four power lines to maximize the potential of dynamic performance, using one
common 5-V power supply for VCC1, VCC2, and VCC3. A 3.3-V power supply for VDD, which is generated from the
5-V power supply for VCC1, VCC2, and VCC3, is recommended to avoid unexpected power supply trouble like
latch-up or power supply sequencing problems.
To maximize the dynamic performance of the PCM3052A, the analog and digital grounds are not connected
internally. These points should have low impedance to avoid digital noise and signal components feeding back
into the analog ground. They should be connected directly to each other under the parts to reduce the potential
of noise problems.
A 0.22-
F electrolytic capacitor is recommended as an ac-coupling capacitor, which gives a 5-Hz cutoff
frequency at PGA gain = 0 dB. If higher full-scale input voltage is required, it can be adjusted by adding only one
series resistor to VINX pins.
Both 0.1-
F ceramic and 10-F electrolytic capacitors are recommended from V
REF1 and VREF2 to AGND1, and
from VCOM to AGND2, to ensure low source impedance of the ADC and DAC references. These capacitors
should be located as close as possible to the VREF1, VREF2, and VCOM pins to reduce dynamic errors on the ADC
and DAC references.
A 10-
F electrolytic capacitor is recommended between MBIAS and AGND3 to ensure low noise on MBIAS.
Both 0.1-
F ceramic and 10-F electrolytic capacitors are recommended between REFO and AGND1 to ensure
low noise on REFO.
A 1-
F non-polar electrolytic capacitor which gives a 27-Hz cutoff frequency, is recommended as coupling
capacitor.
The quality of SCKI can influence dynamic performance, as the PCM3052A (both of DAC and ADC) operates
based on SCKI. Therefore, it might be necessary to consider the jitter, duty, rise and fall time, etc. of the system
clock.
For power-down ON/OFF control without click noise which is generated by DAC output dc level changes, the
external mute control is generally required. The control sequence, which is described as External Mute ON,
CODEC Power Down ON, SCKI stop and resume if necessary, CODEC Power Down OFF, and External Mute
OFF, is recommended.
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