参数资料
型号: PCZ34670EG
厂商: FREESCALE SEMICONDUCTOR INC
元件分类: 稳压器
英文描述: SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO20
封装: 1.27 PITCH, ROHS COMPLIANT, PLASTIC, MS-013AC, SOIC-20
文件页数: 4/24页
文件大小: 986K
代理商: PCZ34670EG
Analog Integrated Circuit Device Data
12
Freescale Semiconductor
34670
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
POWER DEVICES (PD) INTERFACE
The PD interface of the 34670 has been designed to
comply with the requirements of the IEEE standard 802.3af.
The device operates in three different modes, depending on
the input voltage.
PD OPERATING MODES
The IEEE 802.3af standard defines three operating modes
in general. These modes are summarized in Table 5.
SIGNATURE RESISTOR DETECTION
A PD shall present a valid detection signature at the PD
input connector to get properly detected as a power over LAN
enabled pin. Valid and non-valid detection signature regions
are separated by guard bands. See Figure 9 for valid and
non-valid signature regions.
Figure 9. Signature Resistance Guard Bands
The effective resistance across the input pins is calculated
by two subsequent voltage-current measurements made
during the detection process by the PSE.
VALID PD DETECTION SIGNATURE
CHARACTERISTICS
During signature detection phase the Power Sourcing
Equipment (PSE) applies a voltage in the range 2.7 V -
10.1 V on the PI connector and looks for the 25 k
signature
resistor. Since the PD circuitry includes bridge rectifiers, the
PD has to compensate for the voltage drop across the diodes
and the diodes serial resistance. The effective signature
resistance dR is obtained by the V-I-Slope measurement of
the PSE (Figure 10).
It can be seen in Figure 11, that a signature resistor of
25 k
as defined in IEEE 802.3af and two diodes in series
would lead to an effective resistance out of the valid region
specified in Figure 9. At low voltages the effective resistance
is above the maximum allowed value of 26.25 k
, as
illustrated in Figure 11. Therefore one has to adjust the
signature resistor RSIG (R1 and R2, see UVLO Adjustment
on page 13) to a value below 25 k
to stay within the valid
region.
Figure 11. dR at Low Input Voltages
Table 5. PD Operating Modes
Operating Mode
Voltage at PD Input Connector
Signature Resistor Detection
2.7 V - 10.1 V
Classification
14.5 V - 20.5 V
Normal Operation Mode
37 V - 57 V
Signature [k
]
non-valid region
12
23.75 26.25
45
non-valid region
valid region
I
V
I
1
I
2
V
1
V
2
R
d
V
2
V
1
I
2
I
1
---------------------
=
Figure 10. dR Measurement
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