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参数资料
| 型号： | PCZ34670EG |
| 厂商： | FREESCALE SEMICONDUCTOR INC |
| 元件分类： | 稳压器 |
| 英文描述： | SWITCHING REGULATOR, 400 kHz SWITCHING FREQ-MAX, PDSO20 |
| 封装： | 1.27 PITCH, ROHS COMPLIANT, PLASTIC, MS-013AC, SOIC-20 |
| 文件页数： | 8/24页 |
| 文件大小： | 986K |
| 代理商： | PCZ34670EG |
Analog Integrated Circuit Device Data
16
Freescale Semiconductor
34670
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
This reduces power dissipation in the device and improves
overall efficiency.
Figure 17. VDD and MOSFET Driver Output Behavior
A load capacitor connected to VDD ensures a proper
filtering of the VDD voltage. The minimum capacitance value
for this load capacitor should be at least 10
F. An electrolytic
type capacitor is sufficient.
Please refer to application note A/N3279 for further
information about the size of the capacitor.
If VDD falls below the UVLO threshold, the voltage
regulator is
disabled and the MOSFET driver output (GATE)
is held low.
PWM CONTROLLER UVLO, SOFT-START, AND
SHUTDOWN FUNCTION
The soft-start function provided by the 34670 allows the
output voltage to ramp up in a controlled way, thus
eliminating output voltage overshoot.
While the PWM controller is in undervoltage lockout, the
capacitor CSS connected to the SS pin is fully discharged.
After coming out of undervoltage lockout, an internal current
source starts charging the capacitor CSS to initiate soft-start.
When VSS has reached 0.6 V, the gate driver is enabled and
PWM operation begins. The duty cycle during soft-start is
primarily controlled by the internal sawtooth voltage and the
voltage at the SS pin. If the voltage at the SS pin is above
2.6 V, the regular PWM control through pins CS, COMP, and
FB takes over and soft-start is finished.
The following equation calculates the total soft-start time:
OVERVOLTAGE SHUTDOWN
The 34670 includes an overvoltage protection (OVP)
feature that turns off the external MOSFET when the input
voltage exceeds the overvoltage threshold.
When the overvoltage protection is triggered
(VPWR > VOV(R)), the gate driver is immediately disabled. At
the same time, the slow discharge of CSS is initiated. While
the soft-start capacitor is discharging, the gate driver remains
disabled. Once VSS = 0.3 V and the overvoltage
(VPWR < VOV(F)) condition disappears, operation resumes
through a regular soft-start.
CURRENT-SENSE COMPARATOR
The current-sense (CS) comparators and its associated
circuitry limits the peak current through the MOSFET. Current
is sensed at CS pin as a voltage across the sense resistor
RCS between the source of the MOSFET and VOUT.
The CS input has two voltage trip levels, a 600mV high
limit and a 400 mV low limit. When the voltage on CS
produced by a current through the current sense resistor
exceeds the high limit threshold, the current ON-cycle is
immediately terminated and the GATE output is pulled low.
If the low limit threshold is exceeded for longer than 50 ns
(typical blanking time), the current ON-cycle is also
terminated. The blanking time ensures a false termination of
the switching cycle caused by the leading-edge spike on the
sense waveform.
The current-sense resistor RCS is selected according to
the following equation:
where ILIM(primary) is the maximum peak primary-side
current.
In case of an overcurrent in the external MOSFET the
current switching cycle is terminated and GATE is pulled low.
The soft-start capacitor CSS is discharged and after removal
of the faulty condition the PWM is re-started through a regular
soft start.
PWM OSCILLATOR
A default 250 kHz oscillator sets the switching frequency
of the PWM controller. The frequency of the oscillator can be
adjusted between 100 kHz and 400 kHz by an optional
external resistor RFREQ connected from the FREQ pin of the
integrated circuit to VIN.
The appropriate switching frequency fPWM can be
calculated as shown below:
where fPWM is the PWM switching frequency and RFREQ is the
frequency adjusting resistor.
To use the default frequency of 250 kHz the FREQ pin can
be connected to VIN or can be left open.
RESET OUTPUT
The RESET pin is an open drain output. The reset control
circuit supervises the FB voltage and recognizes if the output
HVReg enable
GATE enable
10
2
4
6
8
VGATE(R)
VREG(OFF)
12
VGATE(F)
V
DD
t
SS
ms
[]
0.4 C
SS
nF
[]
=
R
CS
400mV
I
LIM primary
()
----------------------------------------
=
f
PWM
kHz
[]
47920
R
FREQ
k
[]
------------------------------------4
+
=
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