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参数资料
| 型号： | PDI1394P11BD-S |
| 厂商： | NXP SEMICONDUCTORS |
| 元件分类： | Buffer和线驱动 |
| 英文描述： | TRIPLE LINE TRANSCEIVER, PQFP64 |
| 文件页数： | 6/20页 |
| 文件大小： | 148K |
| 代理商： | PDI1394P11BD-S |
Philips Semiconductors
Product specification
PDI1394P11
3-port physical layer interface
1999 Apr 09
14
19.2.4
Other Requests and LREQ
The three bit Request Type field has the following possible values:
BIT(S)
NAME
DESCRIPTION
000
ImmReq
Immediate request: Upon detection of an idle, take control of the bus immediately (no arbitration)
001
IsoReq
Isochronous request: Arbitrate for the bus, no gaps
010
PriReq
Priority request: Arbitrate after a subaction gap, ignore fair protocol
011
FairReq
Fair request: Arbitrate after a subaction gap, follow fair protocol
100
RdReg
Return the specified register contents through a status transfer
101
WrReg
Write to the specified register
110, 111
Reserved
19.3
Operation of LREQ
SV00232
LR0
LR1
LR2
LR3
LR(n–2)
LR(n–1)
Figure 6.
LREQ Input Sequence (each cell represents one SYSCLK sample time)
For fair or priority access, the link requests control of the bus at least
one clock after the phy-link interface becomes idle. If the link senses
that the CTL pins are in a receive state (CTL[0:1] = 10), then it will
know that its request has been lost. This is true anytime during or
after the link sends the bus request transfer. Additionally, the phy will
ignore any fair or priority requests if it asserts the receive state while
the link is requesting the bus. The link will then reissue the request
one clock after the next interface idle.
The cycle master uses a normal priority request to send a cycle start
message. After receiving a cycle start, the link can issue an
isochronous bus request. When arbitration is won, the link proceeds
with the isochronous transfer of data. The isochronous request will
be cleared by the phy once the link sends another type of request or
when the isochronous transfer has been completed.
The ImmReq request is issued when the link needs to send an
acknowledgment after reception of a packet address to it. This
request must be issued during packet reception. This is done to
minimize the delays that a phy would have to wait between the end
of a packet and the transmittal of an acknowledgment. As soon as
the packet ends, the phy immediately grants access of the bus to
the link. the link will send an acknowledgment to the sender unless
the header CRC of the packet turns out to be bad. In this case, the
link will release the bus immediately; it will not be allowed to send
another type of packet on this grant. To guarantee this, the link will
be forced to wait 160 ns after the end of the packet is received. The
phy then gains control of the bus and the ack with the CRC error is
sent. Then the bus is released and allowed to proceed with another
request.
Although highly improbable, it is conceivable that the two separate
nodes will believe that an incoming packet is intended for them. The
nodes then issue a ImmReq request before checking the CRC of the
packet. Since both phys will seize control of the bus at the same
time, a temporary, localized collision of the bus will occur
somewhere between the competing nodes. This collision would be
interpreted by the other nodes on the network as being a ‘ZZ’ line
state, not a bus reset. As soon as the two nodes check the CRC, the
mistaken node will drop its request and the false line state will be
removed. The only side effect would be the loss of the intended
acknowledgment packet (this will be handled by the higher-layer
protocol).
19.4
Read/Write Requests
When the link requests to read the specified register contents, the
phy will send the contents of the register to the link through a status
transfer. If an incoming packet is received while the phy is
transferring status information to the link, the phy will continue to
attempt to transfer the contents of the register until it is successful.
For write requests, the phy will load the data field into the
appropriately addresses register as soon as the transfer has been
completed. The link will be allowed to request read or write
operations at any time.
19.5
Status
A status transfer is initiated by the phy when it has status
information to transfer to the link. The phy will wait until the interface
is idle before starting the transfer. The transfer is initiated by
asserting the following on the control pins: CTL[0:1] = 01 along with
the first two bits of status information on the D[0:1] pins. The phy
maintains CTL[0:1] = 01 for the duration of status transfer. The phy
may prematurely end a status transfer by asserting something other
than CTL[0:1] = 01 on the control pins. This could be caused by an
incoming packet from another node. The phy will continue to attempt
to complete the transfer until the information has been successfully
transmitted. There must be at least one idle cycle in between
consecutive status transfers.
The phy normally sends just the first four bits of status to the link.
These bits are status flags which are needed by the link state
machines. The phy sends an entire status packet to the link after a
request transfer which contains a read request, or when the phy has
pertinent information to send to the link or transaction layers. The
only defined condition when the phy automatically sends a register
to the link is after self-ID, when it sends the physical-ID register
which contains the new node address.
The definition of the bits in the status transfer are shown below.
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相关代理商/技术参数 |
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| PDI1394P21 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P21BE | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P22 | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:3-port physical layer interface |
| PDI1394P22BD | 制造商:PHILIPS 制造商全称:NXP Semiconductors 功能描述:3-port physical layer interface |
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