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| 型号： | PE43404MLI-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 2/11页 |
| 文件大小： | 0K |
| 描述： | IC RF DSA 4-BIT 75 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 15dB |
| 容差： | ±0.25dB |
| 频率范围： | 0 ~ 2GHz |
| 阻抗： | 75 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1044-6 |
PE43404
Product Specification
Figure 15. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
V DD
Parameter/Conditions
Power supply voltage
Min
-0.3
Max
4.0
Units
V
N/C
RF1
Data
Clock
1
2
3
4
20-lead
QFN
4x4mm
Exposed Solder Pad
15
14
13
12
C8
RF2
P/S
Vss/GND
V I
T ST
P IN
V ESD
Voltage on any input
Storage temperature range
Input power (50 ? )
ESD voltage (Human Body
Model)
-0.3
-65
V DD +
0.3
150
+30
500
V
°C
dBm
V
LE
5
11
GND
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be restricted
to the limits in the Operating Ranges table.
Operation between operating range maximum and
absolute maximum for extended periods may reduce
Table 2. Pin Descriptions
reliability.
Pin
No.
Pin
Name
Description
Table 4. Operating Ranges
1
2
3
N/C
RF1
Data
No connect
RF port (Note 1).
Serial interface data input (Note 4).
Parameter
V DD Power Supply
Voltage
Min
2.7
Typ
3.0
Max
3.3
Units
V
4
5
6
7
8
9
10
Clock
LE
V DD
N/C
PUP2
V DD
GND
Serial interface clock input.
Latch Enable input (Note 2).
Power supply pin.
No connect
Power-up selection bit.
Power supply pin.
Ground connection.
I DD Power Supply
Current
Digital Input High
Digital Input Low
Digital Input Leakage
Input Power
0.7xV DD
100
0.3xV DD
1
+24
μ A
V
V
μ A
dBm
11
12
13
GND
V ss /
GND
P/S
Ground connection.
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select.
Temperature range -40 85
Electrostatic Discharge (ESD) Precautions
°C
14
15
16
17
18
19
20
Paddle
RF2
C8
C4
C2
GND
C1
GND
GND
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
Ground for proper operation
Ground for proper operation
When handling this UltraCMOS? device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Notes: 1. Both RF ports must be held at 0 V DC or DC blocked with
an external series capacitor.
2. Latch Enable (LE) has an internal 100 k ? resistor to V DD.
3. Connect pin 12 to GND to enable internal negative
voltage generator. Connect pin 12 to V SS (-VDD) to
bypass and disable internal negative voltage generator.
4. Place a 10 k ? resistor in series, as close to pin as
possible to avoid frequency resonance. See “Resistor on
3” paragraph
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
?2008 Peregrine Semiconductor Corp. All rights reserved.
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
Switching Frequency
The PE43404 has a maximum 25 kHz switching rate.
Resistor on Pin 3
A 10 k ? resistor on the input to Pin 3 (see Figure 5)
will eliminate package resonance between the RF
input pin and the digital input. Specified attenuation
error versus frequency performance is dependent
upon this condition.
Document No. 70-0258-02 │ UltraCMOS? RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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