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参数资料
| 型号： | PE43602MLI-Z |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 5/11页 |
| 文件大小： | 0K |
| 描述： | IC RF DSA 6BIT 50 OHM 24-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™, HaRP™ |
| 衰减值： | 31.5dB |
| 容差： | ±0.3dB |
| 频率范围： | 9kHz ~ 5GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 24-VFQFN 裸露焊盘 |
| 其它名称： | 1046-1046-6 |
PE43602
Product Specification
Table 5. Control Voltage
Table 8. Serial Attenuation Word Truth Table
State
Bias Condition
Attenuation Word
Attenuation
Low
High
0 to +1.0 Vdc at 2 μ A (typ)
+2.6 to +5 Vdc at 10 μ A (typ)
D7
L
L
D6
L
L
D5
L
L
D4
L
L
D3
L
L
D2
L
L
D1
L
H
D0
(LSB)
L
L
Setting
RF1-RF2
Reference I.L.
0.5 dB
Table 6. Latch and Clock Specifications
L
L
L
L
L
H
L
L
1 dB
Latch Enable
X
↑
Shift Clock
↑
X
Function
Shift Register Clocked
Contents of shift register
transferred to attenuator core
L
L
L
L
L
L
L
H
L
L
H
L
L
H
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
2 dB
4 dB
8 dB
16 dB
L
H
H
H
H
H
H
L
31.5 dB
Table 7. Parallel Truth Table
Parallel Control Setting
Attenuation
Setting
D6
L
L
L
L
L
L
H
H
D5
L
L
L
L
L
H
L
H
D4
L
L
L
L
H
L
L
H
D3
L
L
L
H
L
L
L
H
D2
L
L
H
L
L
L
L
H
D1
L
H
L
L
L
L
L
H
RF1-RF2
Reference I.L.
0.5 dB
1 dB
2 dB
4 dB
8 dB
16 dB
31.5 dB
Table 9. Serial Register Map
MSB (last in)
LSB (first in)
Q7
D7
Q6
D6
Q5
D5
Q4
D4
Q3
D3
Q2
D2
Q1
D1
Q0
D0
Bits must be set to logic low
Attenuation Word
Attenuation Word is derived directly from the attenuation value. For example, to program the 12.5 dB state:
Attenuation Word: Multiply by 4 and convert to binary → 4 * 12.5 dB → 50 → 00110010
Serial Input: 00110010
Document No. 70-0248-05 │ www.psemi.com
?2008-2009 Peregrine Semiconductor Corp. All rights reserved.
Page 5 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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