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PEB 20550
PEF 20550
Operational Description
Semiconductor Group
106
01.96
3.8
For proper initialization of the ELIC the following procedure is recommended:
Initialization Procedure
3.8.1
A reset pulse can be applied at the RESEX-pin for at least 4 PDC-clock cycles. The reset
pulse sets all registers to their reset values (cf.
chapter 4.1
).
Note that in this state DCL and FSC do not deliver any clock signals.
Hardware Reset
3.8.2
As the EPIC-1 forms the core of the ELIC, it should usually be programmed first.
EPIC
-1 Initialization
3.8.2.1 Register Initialization
The PCM- and CFI-configuration registers (PMOD, PBNR,
…
, CMD1, CMD2,
…
) should
be programmed to the values required for the application. The correct setting of the
PCM- and CFI-registers is important in order to obtain a reference clock (RCL) which is
consistent with the externally applied clock signals.
The state of the operation mode (OMDR:OMS1..0 bits) does not matter for this
programming step.
PMOD =
PCM-mode, timing characteristics, etc.
PBNR
=
Number of bits per PCM-frame
POFD
=
PCM-offset downstream
POFU
=
PCM-offset upstream
PCSR
=
PCM-timing
CMD1
=
CFI-mode, timing characteristics, etc.
CMD2
=
CFI-timing
CBNR
=
Number of bits per CFI-frame
CTAR
=
CFI-offset (time slots)
CBSR
=
CFI-offset (bits)
CSCR
=
CFI-sub channel positions
3.8.2.2 Control Memory Reset
Since the hardware reset does not affect the EPIC-1 memories (Control and Data
Memories), it is mandatory to perform a "software reset" of the CM. The CM-code ’0000’
(unassigned channel) should be written to each location of the CM. The data written to
the CM-data field is then don’t care, e.g. FF
H
.
OMDR:OMS1..0 must be to '00'
B
for this procedure (reset value).
MADR
=
FF
H
MACR
=
70
H
Wait for EPIC.STAR:MAC = 0