PEB 20550
PEF 20550
Functional Description
Semiconductor Group
88
01.96
In order to avoid such a locking situation the time
t
DFS
min. (value in the AMO-register)
has to be greater then the maximum delay
t
CCDD
(for the case "available"
→
"blocked")
plus the delay
t
DCDU
.
For the QUAT-S a value of 0 is recommended for the suspend counter (register SCV).
For the OCTAT-P it is recommended to program
SCV=1 in the case of 2 terminals
SCV=0 if one terminal is used.
See the following diagram:
Figure 45
2.2.8.4 D-Channel Arbiter Co-operating with QUAT-S Circuits
When D-channel multiplexing is used on a S
0
-bus line card, only the transmit channel
selector of the arbiter is used.
The arbiter state machine can be disabled because the QUAT-S offers a self arbitration
mechanism between several S
0
-buses. This feature is implemented by building a wired
OR connection between the different E-channels. As a result, the arbitration function
does not add additional delays. This means that the priority management on the S
0
-bus
(two classes) still may be used, allowing the mixture of signaling and packet data.
Nevertheless, it still can make sense to use the ELIC arbiter in this configuration. The
advantage of using the arbiter is, that if one terminal fails the others will not be blocked.
ITD05842
t
DCDU
CCDD
t
t
DFS
t
DFS min.
LS
FS
LS
EF + RF
FS + EF
RF
End
Start
Start
Abort
Abort
Start
1. Frame
2. Frame
2. Frame
HDLC Frame
From Terminal
At the Arbiter
"Available"
"Blocked"
Passes
Control Channel
D-Channel Arbiter States
FS = Full Selection
LS = Limited Selection
EF = Expect Frame
RF = Receive Frame
t
DFS
t
DFS
min.
t
DCDU
t
CCDD
= Delay for Switch to "Full Selection" (Value in AMO)
= Min. Delay for not Locking Condition I
= D-Channel Delay Upstream
= Control Channel Delay Downstream
Note: If the full selection counter value (AMO : FCC4...0) is not changed from its reset value 00H
then the D-channel arbiter (ASM) skips the state "Limited Selection".
DCDU
t
t
CCDD
CCDD
t
t
CCDD
DFS
t