APPLICATION INFORMATION
FUNCTIONAL DESCRIPTION
V
IN+
AV
DD
GND
V
IN
-
Reference
Current
OP AMP: INPUT STAGE
InputVoltage(V)
InputOffsetV
oltage(
V)
m
80
70
60
50
40
30
20
10
0
1
0
6
2
3
4
5
AV
=5V
DD
www.ti.com ............................................................................................................................................ SBOS424B – MARCH 2008 – REVISED SEPTEMBER 2008
PMOS transistors. The result
of
this
transition
appears as a small input offset voltage transition that
is reflected to the output by the selected PGA gain.
The PGA112/PGA113 and PGA116/PGA117 are
This
transition
may
be
either
increasing
or
single-ended input, single-supply, programmable gain
decreasing, and differs from part to part as described
amplifiers
(PGAs)
with
an
input
multiplexer.
Multiplexer channel selection and gain selection are
possible differences in input offset voltage between
done
through
a
standard
SPI
interface.
The
two different devices when used with AVDD = +5V.
PGA112/PGA113 have a two-channel input MUX and
Because the exact transition region varies from
the PGA116/PGA117 have a 10-channel input MUX.
The PGA112 and PGA116 provide binary gain
specifies an input offset voltage above and below this
selections (1, 2, 4, 8, 16, 32, 64, 128) and the
input transition region.
PGA113 and PGA117 provide scope gain selections
(1, 2, 5, 10, 20, 50, 100, 200). All models use a
split-supply architecture with an analog supply, AVDD,
and
a
digital
supply,
DVDD.
This
split-supply
architecture
allows
for
ease
of
interface
to
analog-to-digital
converters
(ADCs)
and
microcontrollers in mixed-supply voltage systems,
such as where the analog supply is +5V and the
digital
supply
is
+3V.
Four
internal
calibration
channels are provided for system-level calibration.
The channels are tied to GND, 0.9VCAL, 0.1VCAL, and
VREF,
respectively.
VCAL,
an
external
voltage
connected
to
VCAL/CH0,
acts
as
the
system
calibration reference. If VCAL is the system ADC
reference, then gain and offset calibration on the
ADC are easily accomplished through the PGA using
only one MUX input. If calibration is not used, then
VCAL/CH0 can be used as a standard MUX input. All
four versions provide a VREF pin that can be tied to
Figure 68. PGA Rail-to-Rail Input Stage
ground or, for ease of scaling, to midsupply in
single-supply systems where midsupply is used as a
virtual
ground.
The
PGA112/PGA113
offer
a
software-controlled shutdown feature for low standby
power. The PGA116/PGA117 offer both hardware-
and software-controlled shutdown for low standby
power. The PGA112/PGA113 have a three-wire SPI
digital
interface;
the
PGA116/PGA117
have
a
four-wire SPI digital interface. The PGA116/117 also
have daisy-chain capability.
The PGA op amp is a rail-to-rail input and output
(RRIO) single-supply op amp. The input topology
uses two separate input stages in parallel to achieve
rail-to-rail input. As
Figure 68 shows, there is a
PMOS transistor on each input for operation down to
ground; there is also an NMOS transistor on each
Figure 69. VOS versus Input Voltage—Case 1
input in parallel for operation to the positive supply
rail. When the common-mode input voltage (that is,
the
single-ended
input,
because
this
PGA
is
configured internally for noninverting gain) crosses a
level that is typically about 1.5V below the positive
supply, there is a transition between the NMOS and
Copyright 2008, Texas Instruments Incorporated
29