参数资料
型号: PI2EQX5804CNJE
厂商: Pericom
文件页数: 17/23页
文件大小: 0K
描述: IC PCI-E REDRIVER 100LBGA
标准包装: 176
系列: ReDriver™
类型: 转接驱动器
Tx/Rx类型: CML
电容 - 输入: 50pF
电源电压: 1.15 V ~ 1.25 V
电流 - 电源: 800mA
安装类型: 表面贴装
封装/外壳: 100-BGA
供应商设备封装: 100-LBGA(11x11)
包装: 托盘
3
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe 2.0 ReDriver with
Equalization & Emphasis
Pin #
Pin Name
Type
Description
H5
DE_B
I
De-emphasis enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor. Set high selects output de-emphasis and set low selects
output pre-emphasis.
F8
LB#
I
Input with internal 100K-Ohm pull-up resistor. LB# = High or open for normal
operation. LB# = Low for loopback connection of A_RX to A_TX and B_TX.
G5
MODE
I
Input switch between pin control and I2C control with internal 100k-ohm pull-up
resistor. A LVCMOS high level selects input pin control, and disables I2C opera-
tion. Note, during startup, input status of the control pin (LB#, RESET#, PD#,
RXD_A/B, SEL0-2_A/B, D0-2_A/B, S0-1_A/B, DE_A/B) will be latched to the
initial state of some I2C control pins only once.
C6
PD#
I
Input with internal 100K-Ohm pull-up resistor, PD# =High or open is normal
operation, PD# =Low disable the IC, and set IC to power down mode, both input
and output go Hi-Z.
D6
NC
No Connect
C5
NC
No Connect
J5
RESET#
I
RESET# is an active low channel reset input for Channel A0, B0, A1, B1, A2,
B2, A3 and B3 with internal 100K-Ohm pull-up resistor. When low, the receiver
detection cycle is reset, and normal detection cycle is started after the pin goes
high.
E10
RX50_A
O
Receiver detect output pin for Channel A0. RX50_A=High
indicates that a 50-Ohm termination was sensed at the A0TX+/- outputs.
F1
RX50_B
O
Receiver detect output pin for Channel B0. RX50_B=High
indicates that a 50-Ohm termination was sensed at the B0TX+/- outputs.
E7
RXD_A
I
Receiver detect enable input for Channel A0, A1, A2 and A3 with internal 100K-
Ohm pull-up resistor.
F4
RXD_B
I
Receiver detect enable input for Channel B0, B1, B2 and B3 with internal 100K-
Ohm pull-up resistor.
E6, E8
S[0:1]_A
I
Selection pins for Channel Ax output level (see Output Swing Conguration
Table) w/ 100K-Ohm internal pull up
F5, F3
S[0:1]_B
I
Selection pins for Channel Bx output level (see Output Swing Conguration
Table) w/ 100K-Ohm internal pull up
A5
SCL
I/O
I2C SCL clock input.
A6
SDA
I/O
I2C SDA data input.
E1, E2, E3
SEL[0:2]_A
I
Selection pins for Channel Ax equalization (see Equalizer Conguration Table)
w/ 100K-Ohm internal pull up
09-0001
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