参数资料
型号: PI2EQX5804CNJE
厂商: Pericom
文件页数: 6/23页
文件大小: 0K
描述: IC PCI-E REDRIVER 100LBGA
标准包装: 176
系列: ReDriver™
类型: 转接驱动器
Tx/Rx类型: CML
电容 - 输入: 50pF
电源电压: 1.15 V ~ 1.25 V
电流 - 电源: 800mA
安装类型: 表面贴装
封装/外壳: 100-BGA
供应商设备封装: 100-LBGA(11x11)
包装: 托盘
14
PS8926B
06/08/09
PI2EQX5804C
5.0Gbps 4-Lane PCIe 2.0 ReDriver with
Equalization & Emphasis
BYTE 6 - Power Down Control (PWR)
PD_xy# =0=channel off/power down, PD_xy# =1=normal operation, Latch from PD# input at startup
Bit
76543210
Name
PD_A0#
PD_B0#
PD_A1#
PD_B1#
PD_A2#
PD_B2#
PD_A3#
PD_B3#
Type
R/W
Power-on
State
PD#
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Power Down Control register allows for individual control over each channel for power savings. When
PD_xy# is logic 0 the channel is turned off. When PD_xy# is 1 then the channel is enabled for normal
operation.
BYTE 7 - Receiver Detect Enable (RXD)
RXD_xy =0=channel off/power down, RXD_xy =1=normal operation, Latch from PD# input at startup
Bit
76543210
Name
RXD_A0
RXD_B0
RXD_A1
RXD_B1
RXD_A2
RXD_B2
RXD_A3
RXD_B3
Type
R/W
Power-on
State
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
RXD_A
RXD_B
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The Receiver Detect Enable register allows for control of the receiver detect state machine for each individual
channel. When RXD_xy is set to 0, then the receiver detect function is disabled. When RXD_xy is logic 1,
then the receiver detect state machine is enabled for operation. The initial state of the register bits are deter-
mined by the RXD_A and RXD_B input pins during power-up.
BYTE 8 - A-Channels Equalizer and Output Control (AEOC)
SELx_A: Equalizer conguration, Dx_A: Emphasis control, Sx_A: Output level control (see Conguration Table)
Bit
76543210
Name
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Type
R/W
Power-on
State
SEL0_A
SEL1_A
SEL2_A
D0_A
D1_A
D2_A
S0_A
S1_A
Note: R=Read only, W=Write only, R/W=Read and Write, X=Undened, rsvd=reserved for future use
The A-Channels Equalizer and Output Control register is used to control the conguration of the input equal-
izer and output emphasis and levels of the four A channels. These register bits are loaded from the input con-
guration pins of the same name at power-on. These bits may be changed if the MODE# input is set to allow
I2C conguration. Please refer to the tables (1) Equalizer Conguration, (2) Output Swing Conguration and
09-0001
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