参数资料
| 型号： | PI74SSTVF16857KE |
| 厂商： | Pericom |
| 文件页数： | 1/9页 |
| 文件大小： | 0K |
| 描述： | IC REG BUFFER 14BIT 48TVSOP |
| 产品变化通告： | Product Discontinuation Notice 29/May/2007 |
| 标准包装： | 50 |
| 系列： | 74SSTVF |
| 逻辑类型： | DDR 的寄存缓冲器 |
| 电源电压： | 2.3 V ~ 2.7 V |
| 位数： | 14 |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TFSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 48-TVSOP |
| 包装： | 管件 |
1
PS8656A
05/27/03
1
2
3
4
5
6
7
8
9
48
10
47
11
46
12
45
13
44
14
43
15
42
16
41
17
40
18
39
19
38
20
37
21
36
22
35
23
34
24
33
32
31
30
29
28
27
26
25
Q1
Q2
GND
VDDQ
Q3
Q4
Q5
GND
VDDQ
Q6
Q7
VDDQ
GND
Q8
Q9
VDDQ
GND
Q10
Q11
Q12
VDDQ
GND
Q13
Q14
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK
VDD
GND
VREF
RESET
D8
D9
D10
D11
D12
VDD
GND
D13
D14
ProductDescription
Pericom Semiconductor’s PI74SSTVF16857 series of logic circuits
are produced using the Company’s advanced sub-micron CMOS
technology, achieving industry leading speed.
The 14-bit PI74SSTVF16857 universal bus driver is designed
for 2.5V to 2.6V VDD operation and SSTL_2 I/O Levels except for
the RESET input which is LVCMOS.
Data flow from D to Q is controlled by the differential clock , CLK,
CLK and RESET. Data is triggered on the positive edge of CLK.
CLK must be used to maintain noise margins.
RESET must be supported with LVCMOS levels as VREF may not
be stable during power-up. RESET is asynchronous and is intended
for power-up only and when low assures that all of the registers reset
to the Low State, Q outputs are low, and all input receivers, data and
clock, are switched off.
Pericom’s PI74SSTVF16857 is characterized for operation from
0° to 70°C.
Product Features
PI74 SSTVF16857 is designed for low-voltage operation,
2.5VforPC1600~PC2700;2.6VforPC3200
Supports SSTL_2 Class I output specifications
SSTL_2 Input and Output Levels
Designed for DDR Memory
Flow-Through Architecture
Packaging Options (Pb-free available):
– 48-pin 240 mil wide plastic TSSOP (A)
– 48-pin 173 mil wide plastic TVSOP (K)
Logic Block Diagram
ProductPinConfiguration
ProductPinDescription
48-Pin
A,K
s
t
u
p
n
Is
t
u
p
t
u
O
T
E
S
E
RK
L
CK
L
CD
Q
LX
X
L
H
↑↓
HH
Η↑
↓
LL
HH
r
o
LH
r
o
LX
o
Q
)
2
(
TruthTable(1)
Notes:
1. H = High Signal Level
L = Low Signal Level
↑ = TransitionLOW-to-HIGH
↓ =TransitionHIGH-to-LOW
X = Irrelevant
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012
PI74SSTVF16857
14-Bit Registered Buffer
2. Output level before the
indicated steady state
input conditions were
established.
TO 13 OTHER CHANNELS
RESET
CLK
38
39
VREF
D1
48
35
D
R
CLK
Q1
1
CLK
V
34
PinName
Description
RESET
Reset (Active Low)
CLK
Clock Input
CLK
Clock Input
D
Data Input
Q
Data Output
GND
Ground
VDD
Core Supply Voltage
VDDQ
Output Supply Voltage
VREF
Input Reference Voltage
相关PDF资料 |
PDF描述 |
|---|---|
| PI74SSTVF16859AE | IC REG BUFFER 13-26BIT 64-TSSOP |
| PI74SSTVF16859AZBE | IC REG BUFFER 13-26BIT 56-QFN |
| PI74STX1G02CX | IC SINGLE 2-IN NOR GATE SC70-5 |
| PI74STX1GU04CEX | IC UNBUFFERED INVERTER SC70-5 |
| PI74STX4G4245ZJEX | IC 2BIT LVL SHFT BUF/TXRX 16TDFN |
相关代理商/技术参数 |
参数描述 |
|---|---|
| PI74SSTVF16857KX | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 14-CH CMOS 48-Pin TVSOP T/R |
| PI74SSTVF16859A | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP Tube |
| PI74SSTVF16859AE | 功能描述:寄存器 13/26B Registered Buffer RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| PI74SSTVF16859AEX | 功能描述:寄存器 13/26B Registered Buffer RoHS:否 制造商:NXP Semiconductors 逻辑类型:CMOS 逻辑系列:HC 电路数量:1 最大时钟频率:36 MHz 传播延迟时间: 高电平输出电流:- 7.8 mA 低电平输出电流:7.8 mA 电源电压-最大:6 V 最大工作温度:+ 125 C 封装 / 箱体:SOT-38 封装:Tube |
| PI74SSTVF16859AX | 制造商:Pericom Semiconductor Corporation 功能描述:Registered Buffer Single 13-CH CMOS 64-Pin TSSOP T/R |
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