参数资料
型号: PIC10F206-E/MC
厂商: Microchip Technology
文件页数: 71/94页
文件大小: 0K
描述: IC PIC MCU FLASH 512X12 8DFN
标准包装: 150
系列: PIC® 10F
核心处理器: PIC
芯体尺寸: 8-位
速度: 4MHz
外围设备: POR,WDT
输入/输出数: 3
程序存储器容量: 768B(512 x 12)
程序存储器类型: 闪存
RAM 容量: 24 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 8-VFDFN 裸露焊盘
包装: 管件
配用: AC164334-ND - MODULE SOCKET FOR 8L 2X3MM DFN
AC163020-2-ND - ADAPTER PROGRAM PIC10F 2X3 DFN
74
AT89/83EB5114
4311C–8051–02/08
Status of the Flash Memory
The bit FBUSY in FCON register is used to indicate the status of programming. FBUSY
is set when programming is in progress.
Loading the Column Latches
Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This
provides the capability to program the whole memory by byte, by page or by any number
of bytes in a page.
When programming is launched, an automatic erase of the locations loaded in the col-
umn latches is first performed, then programming is effectively done. Thus no page or
block erase is needed and only the loaded data are programmed in the corresponding
page.
The following procedure is used to load the column latches and is summarized in
Disable interrupt and map the column latch space by setting FPS bit.
Load the DPTR with the address to load.
Load Accumulator register with the data to load.
Execute the MOVX @DPTR, A instruction.
If needed loop the three last instructions until the page is completely loaded.
unmap the column latch and Enable Interrupt
Figure 34. Column Latches Loading Procedure
Note:
The last page address used when loading the column latch is the one used to select the
page programming address.
Column Latches Loading
Data Load
DPTR= Address
ACC= Data
Exec: MOVX @DPTR, A
Last Byte
to load?
Column Latches Mapping
FPS= 1
Data memory Mapping
FPS= 0
Disable IT
EA= 0
Enable IT
EA= 1
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