参数资料
型号: PIC12C672T-10I/MF
厂商: Microchip Technology
文件页数: 72/129页
文件大小: 0K
描述: IC MCU OTP 2KX14 W/AD 8-DFN
标准包装: 3,300
系列: PIC® 12C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
外围设备: POR,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 带卷 (TR)
配用: AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
1999 Microchip Technology Inc.
DS30561B-page 47
PIC12C67X
The ADRES Register contains the result of the A/D
conversion. When the A/D conversion is complete, the
result is loaded into the ADRES register, the GO/DONE
bit (ADCON0<2>) is cleared, and A/D interrupt flag bit
ADIF (PIE1<6>) is set. The block diagrams of the A/D
module are shown in Figure 8-1.
After the A/D module has been configured as desired,
the selected channel must be acquired before the con-
version is started. The analog input channels must
have their corresponding TRIS bits selected as an
input. To determine sample time, see Section 8.1. After
this acquisition time has elapsed, the A/D conversion
can be started. The following steps should be followed
for doing an A/D conversion:
1.
Configure the A/D module:
Configure analog pins / voltage reference /
and digital I/O (ADCON1 and TRIS)
Select A/D input channel (ADCON0)
Select A/D conversion clock (ADCON0)
Turn on A/D module (ADCON0)
2.
Configure A/D interrupt (if desired):
Clear ADIF bit
Set ADIE bit
Set GIE bit
3.
Wait the required acquisition time.
4.
Start conversion:
Set GO/DONE bit (ADCON0)
5.
Wait for A/D conversion to complete, by either:
Polling for the GO/DONE bit to be cleared
OR
Waiting for the A/D interrupt
6.
Read A/D Result Register (ADRES), clear bit
ADIF if required.
7.
For the next conversion, go to step 1, step 2 or
step 3 as required. The A/D conversion time per
bit is defined as TAD. A minimum wait of 2TAD is
required before next acquisition starts.
FIGURE 8-1:
A/D BLOCK DIAGRAM
(Input voltage)
VIN
VREF
(Reference
voltage)
VDD
PCFG<2:0>
CHS<1:0>
GP4/AN3
GP0/AN0
GP2/AN2
GP1/AN1/VREF
11
10
01
00
A/D
Converter
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