参数资料
型号: PIC12C672T-10I/MF
厂商: Microchip Technology
文件页数: 73/129页
文件大小: 0K
描述: IC MCU OTP 2KX14 W/AD 8-DFN
标准包装: 3,300
系列: PIC® 12C
核心处理器: PIC
芯体尺寸: 8-位
速度: 10MHz
外围设备: POR,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: OTP
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 3 V ~ 5.5 V
数据转换器: A/D 4x8b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 带卷 (TR)
配用: AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
PIC12C67X
DS30561B-page 48
1999 Microchip Technology Inc.
8.1
A/D Sampling Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 8-2. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
The maximum recommended imped-
ance for analog sources is 10 k
. After the analog
input channel is selected (changed), this acquisition
must be done before the conversion can be started.
To calculate the minimum acquisition time, Equation 8-1
may be used. This equation assumes that 1/2 LSb error
is used (512 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
EQUATION 8-1:
A/D MINIMUM CHARGING
TIME
VHOLD = (VREF - (VREF/512)) (1 - e(-Tc/C
HOLD
(RIC + RSS + RS)))
or
Tc = -(51.2 pF)(1 k
+ RSS + RS) ln(1/511)
Example 8-1 shows the calculation of the minimum
required acquisition time TACQ. This calculation is
based on the following system assumptions.
Rs = 10 k
1/2 LSb error
VDD = 5V
→ Rss = 7 k
Temp (system max.) = 50
°C
VHOLD = 0 @ t = 0
EXAMPLE 8-1:
CALCULATING THE
MINIMUM REQUIRED
SAMPLE TIME
TACQ = Internal Amplifier Settling Time +
Holding Capacitor Charging Time +
Temperature Coefficient
TACQ =5
s + Tc + [(Temp - 25°C)(0.05 s/°C)]
TC =-CHOLD (RIC + RSS + RS) ln(1/512)
-51.2 pF (1 k
+ 7 k + 10 k) ln(0.0020)
-51.2 pF (18 k
) ln(0.0020)
-0.921
s (-6.2146)
5.724
s
TACQ =5
s + 5.724 s + [(50°C - 25°C)(0.05 s/°C)]
10.724
s + 1.25 s
11.974
s
Note 1: The reference voltage (VREF) has no
effect on the equation, since it cancels
itself out.
2: The charge holding capacitor (CHOLD) is
not discharged after each conversion.
3: The maximum recommended impedance
for analog sources is 10 k
. This is
required to meet the pin leakage specifi-
cation.
4: After a conversion has completed, a
2.0 TAD delay must
complete before
acquisition can begin again. During this
time, the holding capacitor is not con-
nected to the selected A/D input channel.
FIGURE 8-2:
ANALOG INPUT MODEL
CPIN
VA
Rs
RAx
5 pF
VDD
VT = 0.6V
I leakage
RIC
≤ 1k
Sampling
Switch
SS
Rss
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
( k
)
VDD
= 51.2 pF
± 500 nA
Legend: CPIN
VT
I leakage
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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