参数资料
型号: PIC12F635-I/P
厂商: Microchip Technology
文件页数: 25/74页
文件大小: 0K
描述: IC MCU FLASH 1KX14 8DIP
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 60
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 5
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
包装: 管件
产品目录页面: 637 (CN2011-ZH PDF)
配用: DM163029-ND - BOARD PICDEM FOR MECHATRONICS
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
ACICE0201-ND - MPLABICE 8P 300 MIL ADAPTER
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
Micrel, Inc.
KSZ8841-PMQL
October 2007
31
M9999-100407-1.5
Configuration Revision Register (CFRV Offset 08H)
The CFRV register contains the KSZ8841-PMQL revision number. The following table shows the CFRV register bit
fields.
Bit
Default
Description
31 - 24
0x02
Base Class
Indicates the network controller, and is equal to 0x2.
23 - 16
0x00
Subclass
Indicates the Fast/Gigabit Ethernet chip, and is equal to 0x00.
15 - 8
0x00
Reserved
7 - 4
0x1
Revision Number
Indicates the KSZ8841-PMQL revision number, and is equal to 0x1. This
number is incremented for subsequent revision.
3 - 0
0x0
Step Number
Indicates the KSZ8841-PMQL step number, and is equal to 0x0 (chip
revision A). This number is incremented for subsequent KSZ8841-PMQL
steps within the current revision.
Configuration Latency Timer Register (CFLT Offset 0CH)
This register configures the cache line size field and the latency timer.
The following table shows the CFLT register bit fields.
Bit
Default
Description
31 - 16
0x00
Reserved
15 - 8
0x00
Configuration Latency Timer
Specifies, in units of PCI bus clocks, the value of the latency timer of the
KSZ8841-PMQL. When the KSZ8841-PMQL asserts FRAME_N, it enables
its latency timer to count. If the KSZ8841-PMQL deserts FRAME_N prior to
count expiration, the content of the latency timer is ignored. Otherwise,
after the count expires, the KSZ8841-PMQL initiates transaction
termination as soon as its GNT_N is deserted.
7 - 0
0x00
Cache Line Size
Specifies, in unit of 32-bit words(Dword), the system cache line size.
Configuration Base Memory Address Register (CBMA Offset 10H)
The CBMA register specifies the base memory address for accessing the KSZ8841-PMQL CSRs. This register must be
initialized prior to accessing any CSR with memory access.
The following table shows the CBMA register bit fields.
Bit
Default
Description
31 - 11
0
Configuration Base Memory Address
Defines the base address assigned for mapping the KSZ8841-PMQL
CSRs.
10 - 1
0
This field value is 0 when read.
0
Memory Space Indicator
Determines that the register maps into the Memory space.
The value in this field is 0.
This is a read-only field.
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