参数资料
型号: PIC12F635T-I/MF
厂商: Microchip Technology
文件页数: 29/74页
文件大小: 0K
描述: IC MCU FLASH 1KX14 8DFN
标准包装: 3,300
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 5
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 带卷 (TR)
配用: AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
Micrel, Inc.
KSZ8841-PMQL
October 2007
35
M9999-100407-1.5
Power-Management Control and Status Register (CPMC Offset 54H)
The CMPC register is a power-management control and status register. This register can control and sate power
management events. The following table shows the CMPC register bit fields.
Bit
Default
Description
31 - 16
0x0000
Reserved
15
0
PME_Status
This bit indicates that the KSZ8841-PMQL has detected a power-
management event. If bit PME_Enable is set, the KSZ8841-PMQL also
asserts the PME_N pin. This bit is cleared on power-up reset or by write
1. It is not modified by either hardware or software reset. When this bit is
cleared, the KSZ8841-PMQL deserts the PME_N pin.
14 - 9
0x00
Reserved
8
0
PME_Enable
If this bit is set, the KSZ8841-PMQL can assert the PME_N pin.
Otherwise, assertion of the PME_N pin is disabled. This bit is cleared on
power-up reset only and is not modified by either hardware or software
reset.
7 - 4
0x0
Reserved
3
0
No Soft Reset
If this bit is set (“1”), the KSZ8841-PMQL does not perform an internal
reset when transitioning from D3_hot to D0 because of PowerState
commands. Configuration context is preserved. Upon transition from
D3_hot to the D0 Initialized state, no additional operating system
intervention is required to preserve configuration context beyond writing
the PowerState bits.
If this bit is cleared (“0”), the KSZ8841-PMQL does perform an internal
reset when transitioning from D3_hot to D0 via software control of the
PowerState bits. Configuration context is lost when performing the soft
reset. Upon transition from D3_hot to the D0 state, full reinitialization
sequence is needed to return the device to D0 Initialized.
Regardless of this bit, devices that transition from D3_hot to D0 by a
system or bus segment reset will return to the device state D0
Uninitialized with only PME context preserved if PME is supported and
enabled.
2
0
Reserved
1 - 0
00
Power State
This field is used to set the current power state of the KSZ8841-PMQL
and to determine its power state. The definitions of the field values are:
0: D0
1: D1
2: D2
3: D3(hot)
This field gets a value of 0 after power up.
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