参数资料
型号: PIC12F635T-I/MF
厂商: Microchip Technology
文件页数: 33/74页
文件大小: 0K
描述: IC MCU FLASH 1KX14 8DFN
标准包装: 3,300
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 5
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: 闪存
EEPROM 大小: 128 x 8
RAM 容量: 64 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 带卷 (TR)
配用: AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
AC162057-ND - MPLAB ICD 2 HEADER 14DIP
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
Micrel, Inc.
KSZ8841-PMQL
October 2007
39
M9999-100407-1.5
MAC DMA Receive Start Command Register (MDRSC Offset 0x000C)
This register is written by the CPU when there are frame data in receive buffer to be processed.
The following table shows the register bit fields.
Bit
Default \
Read/
Write
Description
31 - 0
0x00000000
WO
WRSC Receive Start Command
When written with any value, the Receive DMA checks for descriptors
to be acquired. If no descriptor is available, the receive process returns
to suspended state and wait for the next receive restart command. If
descriptors are available, the receive process resumes. This bit is self-
clearing.
Transmit Descriptor List Base Address Register (TDLB Offset 0x0010)
This register is used for Transmit descriptor list base address register. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not word-
aligned.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31 - 0
0x00000000
RW
WSTL Start of Transmit List
Note: Write can only occur when the transmit process stopped.
Receive Descriptor List Base Address Register (RDLB Offset 0x0014)
This register is used for Receive descriptor list base address register. The register is used to point to the start of the
appropriate descriptor list. Writing to this register is permitted only when its respective process is in the stopped state.
When stopped, the register must be written before the respective START command is given.
Note: The descriptor lists must be Word (32-bit) aligned. The KSZ8841-PMQL behavior is unpredictable when the lists are not word-
aligned.
The following table shows the register bit fields.
Bit
Default
Read/
Write
Description
31 - 0
0x00000000
RW
WSRL Start of Receive List
Note: Write can only occur when the transmit process stopped.
MAC Multicast Table 0 Register (MTR0 Offset 0x0020)
The 64 bit multicast table is used for group address filtering. The value is defined as the six most significant bits of the
CRC of the DA. The two most significant bits select the register to be used, while the other determines the bit within the
register.
Bit
Default
Read/
Write
Description
31-0
0x00000000
RW
MTR0 Multicast Table 0
When appropriate bit is set, the packet received with DA matches the
CRC hashing function is received without being filtered.
Note: when receive all (RXRA) or receive multicast (RXRM) bit is set in
the RXCR then all multicast addresses are received regardless of the
multicast table value.
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