参数资料
型号: PIC12F683T-E/MF
厂商: Microchip Technology
文件页数: 149/176页
文件大小: 0K
描述: IC MCU FLASH 2KX14 8DFN
Digi-Key 应用说明: AN0005 PWM Example with Microchip's CCP Module
AN0005 Example Code
标准包装: 3,300
系列: PIC® 12F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 5
程序存储器容量: 3.5KB(2K x 14)
程序存储器类型: 闪存
EEPROM 大小: 256 x 8
RAM 容量: 128 x 8
电压 - 电源 (Vcc/Vdd): 2 V ~ 5.5 V
数据转换器: A/D 4x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 8-VDFN 裸露焊盘
包装: 带卷 (TR)
配用: AC164324-ND - MODULE SKT FOR MPLAB 8DFN/16QFN
XLT08DFN2-ND - SOCKET TRANSITION ICE 14DIP/8DFN
AC162058-ND - HEADER MPLAB ICD2 FOR PIC12F683
I3-DB12F683-ND - BOARD DAUGHTER ICEPIC3
XLT08DFN-ND - SOCKET TRANSITION ICE 8DFN
AC164032-ND - ADAPTER PICSTART PLUS 8DFN/DIP
AC124001-ND - MODULE SKT PROMATEII 8DIP/SOIC
PIC12F683
DS41211D-page 72
2007 Microchip Technology Inc.
10.1
EECON1 and EECON2 Registers
EECON1 is the control register with four low-order bits
physically implemented. The upper four bits are non-
implemented and read as ‘0’s.
Control bits RD and WR initiate read and write,
respectively. These bits cannot be cleared, only set in
software. They are cleared in hardware at completion
of the read or write operation. The inability to clear the
WR bit in software prevents the accidental, premature
termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset during normal
operation. In these situations, following Reset, the user
can check the WRERR bit, clear it and rewrite the
location. The data and address will be cleared.
Therefore, the EEDAT and EEADR registers will need
to be re-initialized.
Interrupt flag, EEIF bit of the PIR1 register, is set when
write is complete. This bit must be cleared in software.
EECON2 is not a physical register. Reading EECON2
will read all ‘0’s. The EECON2 register is used
exclusively in the data EEPROM write sequence.
Note:
The
EECON1,
EEDAT
and
EEADR
registers should not be modified during a
data EEPROM write (WR bit = 1).
REGISTER 10-3:
EECON1: EEPROM CONTROL REGISTER
U-0
R/W-x
R/W-0
R/S-0
WRERR
WREN
WR
RD
bit 7
bit 0
Legend:
S = Bit can only be set
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7-4
Unimplemented: Read as ‘0’
bit 3
WRERR: EEPROM Error Flag bit
1
= A write operation is prematurely terminated (any MCLR Reset, any WDT Reset during
normal operation or BOR Reset)
0
= The write operation completed
bit 2
WREN: EEPROM Write Enable bit
1
= Allows write cycles
0
= Inhibits write to the data EEPROM
bit 1
WR: Write Control bit
1
= Initiates a write cycle (The bit is cleared by hardware once write is complete. The WR bit can only
be set, not cleared, in software.)
0
= Write cycle to the data EEPROM is complete
bit 0
RD: Read Control bit
1
= Initiates an EEPROM read (Read takes one cycle. RD is cleared in hardware. The RD bit can only
be set, not cleared, in software.)
0
= Does not initiate an EEPROM read
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