参数资料
型号: PIC16C711-20E/P
厂商: Microchip Technology
文件页数: 171/177页
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D 18DIP
产品培训模块: Asynchronous Stimulus
标准包装: 25
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 13
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: OTP
RAM 容量: 68 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
数据转换器: A/D 4x8b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 18-DIP(0.300",7.62mm)
包装: 管件
93
7593L–AVR–09/12
AT90USB64/128
Note:
1. n = 3, 2, 1or 0.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
12.0.2
EICRB – External Interrupt Control Register B
Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Interrupt 7 - 4 Sense Control Bits
The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the
corresponding interrupt mask in the EIMSK is set. The level and edges on the external pins that
activate the interrupts are defined in Table 12-3. The value on the INT7:4 pins are sampled
before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one
clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an inter-
rupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL
divider is enabled. If low level interrupt is selected, the low level must be held until the comple-
tion of the currently executing instruction to generate an interrupt. If enabled, a level triggered
interrupt will generate an interrupt request as long as the pin is held low.
Note:
1. n = 7, 6, 5 or 4.
When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt
Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.
12.0.3
EIMSK – External Interrupt Mask Register
Table 12-1.
Interrupt sense control (1).
ISCn1
ISCn0
Description
00
The low level of INTn generates an interrupt request.
0
1
Any edge of INTn generates asynchronously an interrupt request.
1
0
The falling edge of INTn generates asynchronously an interrupt request.
1
The rising edge of INTn generates asynchronously an interrupt request.
Table 12-2.
Asynchronous external interrupt characteristics.
Symbol
Parameter
Condition
Min.
Typ.
Max.
Units
tINT
Minimum pulse width for asynchronous
external interrupt
50
ns
Bit
7
65
43
21
0
ISC71
ISC70
ISC61
ISC60
ISC51
ISC50
ISC41
ISC40
EICRB
Read/write
R/W
Initial value
00
Table 12-3.
Interrupt sense control
ISCn1
ISCn0
Description
00
The low level of INTn generates an interrupt request.
0
1
Any logical change on INTn generates an interrupt request.
1
0
The falling edge between two samples of INTn generates an interrupt request.
1
The rising edge between two samples of INTn generates an interrupt request.
Bit
7
65
43
21
0
INT7
INT6
INT5
INT4
INT3
INT2
INT1
IINT0
EIMSK
Read/write
R/W
Initial value
00
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