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参数资料
型号： PIC16C711-20E/P
厂商： Microchip Technology
文件页数： 46/177页
文件大小： 0K
描述： IC MCU OTP 1KX14 A/D 18DIP
产品培训模块： Asynchronous Stimulus
标准包装： 25
系列： PIC® 16C
核心处理器： PIC
芯体尺寸： 8-位
速度： 20MHz
外围设备： 欠压检测/复位，POR，WDT
输入/输出数： 13
程序存储器容量： 1.75KB（1K x 14）
程序存储器类型： OTP
RAM 容量： 68 x 8
电压 - 电源 (Vcc/Vdd)： 4 V ~ 6 V
数据转换器： A/D 4x8b
振荡器型： 外部
工作温度： -40°C ~ 125°C
封装/外壳： 18-DIP（0.300"，7.62mm）
包装： 管件
PIC16C71X
DS30272A-page 14
1997 Microchip Technology Inc.
4.2.2
SPECIAL FUNCTION REGISTERS
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The special function registers can be classied into two
sets (core and peripheral). Those registers associated
with the “core” functions are described in this section,
and those related to the operation of the peripheral fea-
tures are described in the section of that peripheral
feature.
TABLE 4-1:
PIC16C710/71/711 SPECIAL FUNCTION REGISTER SUMMARY
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on:
POR,
BOR
Value on all
other resets
(1)
Bank 0
00h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
01h
TMR0
Timer0 module’s register
xxxx xxxx
uuuu uuuu
02h(3)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
03h(3)
STATUS
IRP(5)
RP1(5)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
04h(3)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
05h
PORTA
—
PORTA Data Latch when written: PORTA pins when read
---x 0000
---u 0000
06h
PORTB
PORTB Data Latch when written: PORTB pins when read
xxxx xxxx
uuuu uuuu
07h
—
Unimplemented
—
08h
ADCON0
ADCS1
ADCS0
(6)
CHS1
CHS0
GO/DONE
ADIF
ADON
00-0 0000
09h(3)
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
0Ah(2,3)
PCLATH
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
0Bh(3)
INTCON
GIE
ADIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Bank 1
80h(3)
INDF
Addressing this location uses contents of FSR to address data memory (not a physical register)
0000 0000
81h
OPTION
RBPU
INTEDG
T0CS
T0SE
PSA
PS2
PS1
PS0
1111 1111
82h(3)
PCL
Program Counter's (PC) Least Signicant Byte
0000 0000
83h(3)
STATUS
IRP(5)
RP1(5)
RP0
TO
PD
Z
DC
C
0001 1xxx
000q quuu
84h(3)
FSR
Indirect data memory address pointer
xxxx xxxx
uuuu uuuu
85h
TRISA
—
PORTA Data Direction Register
---1 1111
86h
TRISB
PORTB Data Direction Control Register
1111 1111
87h(4)
PCON
—
POR
BOR
---- --qq
---- --uu
88h
ADCON1
—
PCFG1
PCFG0
---- --00
89h(3)
ADRES
A/D Result Register
xxxx xxxx
uuuu uuuu
8Ah(2,3)
PCLATH
—
Write Buffer for the upper 5 bits of the Program Counter
---0 0000
8Bh(3)
INTCON
GIE
ADIE
T0IE
INTE
RBIE
T0IF
INTF
RBIF
0000 000x
0000 000u
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Shaded locations are unimplemented, read as ‘0’.
Note 1:
Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
2:
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
contents are transferred to the upper byte of the program counter.
3:
These registers can be addressed from either bank.
4:
The PCON register is not physically implemented in the PIC16C71, read as ’0’.
5:
The IRP and RP1 bits are reserved on the PIC16C710/71/711, always maintain these bits clear.
6:
Bit5 of ADCON0 is a General Purpose R/W bit for the PIC16C710/711 only. For the PIC16C71, this bit is unimplemented,
read as '0'.
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