参数资料
型号: PIC16C711-20E/P
厂商: Microchip Technology
文件页数: 45/177页
文件大小: 0K
描述: IC MCU OTP 1KX14 A/D 18DIP
产品培训模块: Asynchronous Stimulus
标准包装: 25
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
外围设备: 欠压检测/复位,POR,WDT
输入/输出数: 13
程序存储器容量: 1.75KB(1K x 14)
程序存储器类型: OTP
RAM 容量: 68 x 8
电压 - 电源 (Vcc/Vdd): 4 V ~ 6 V
数据转换器: A/D 4x8b
振荡器型: 外部
工作温度: -40°C ~ 125°C
封装/外壳: 18-DIP(0.300",7.62mm)
包装: 管件
139
7593L–AVR–09/12
AT90USB64/128
Note:
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the WGMn2:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
15.10.3
TCCR1B – Timer/Counter1 Control Register B
15.10.4
TCCR3B – Timer/Counter3 Control Register B
Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap-
ture function is disabled.
Bit 5 – Reserved bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
Bit 4:3 – WGMn3:2: Waveform Generation mode
See TCCRnA Register description.
11
1
0
1
PWM, phase correct
OCRnA
TOP
BOTTOM
12
1
0
CTC
ICRn
Immediate
MAX
13
110
1
(Reserved)
14
1
0
Fast PWM
ICRn
TOP
15
1
Fast PWM
OCRnA
TOP
Table 15-4.
Waveform Generation mode bit description
(1). (Continued)
Mode
WGMn3
WGMn2
(CTCn)
WGMn1
(PWMn1)
WGMn0
(PWMn0)
Timer/Counter mode of
operation
TOP
Update of
OCRn
x at
TOVn flag
set on
Bit
7
65
4
3
21
0
ICNC1
ICES1
WGM13
WGM12
CS12
CS11
CS10
TCCR1B
Read/write
R/W
R
R/W
Initial value
0
Bit
7654
3
2
10
ICNC3
ICES3
WGM33
WGM32
CS32
CS31
CS30
TCCR3B
Read/write
R/W
R
R/W
Initial value
0000
0
00
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