参数资料
型号: PIC16C765-I/PT
厂商: Microchip Technology
文件页数: 10/165页
文件大小: 0K
描述: IC MCU OTP 8KX14 USB 44TQFP
产品培训模块: Asynchronous Stimulus
8-bit PIC® Microcontroller Portfolio
标准包装: 160
系列: PIC® 16C
核心处理器: PIC
芯体尺寸: 8-位
速度: 24MHz
连通性: SCI,UART/USART,USB
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 33
程序存储器容量: 14KB(8K x 14)
程序存储器类型: OTP
RAM 容量: 256 x 8
电压 - 电源 (Vcc/Vdd): 4.35 V ~ 5.25 V
数据转换器: A/D 8x8b
振荡器型: 外部
工作温度: -40°C ~ 85°C
封装/外壳: 44-TQFP
包装: 托盘
产品目录页面: 636 (CN2011-ZH PDF)
配用: XLT44PT3-ND - SOCKET TRAN ICE 44MQFP/TQFP
AC164305-ND - MODULE SKT FOR PM3 44TQFP
ISPICR1-ND - ADAPTER IN-CIRCUIT PROGRAMMING
444-1001-ND - DEMO BOARD FOR PICMICRO MCU
AC164020-ND - MODULE SKT PROMATEII 44TQFP
2000 Microchip Technology Inc.
Preliminary
DS41124C-page 107
PIC16C745/765
13.6
Interrupts
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all unmasked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous
registers.
Individual
interrupt
bits
are
set,
regardless of the status of the GIE bit. The GIE bit is
cleared on RESET.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit, which
re-enables interrupts.
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the spe-
cial function registers PIR1 and PIR2. The correspond-
ing interrupt enable bits are contained in special
function registers PIE1 and PIE2 and the peripheral
interrupt enable bit is contained in special function reg-
ister INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack, and the PC is loaded
with 0004h. Once in the Interrupt Service Routine, the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends when the interrupt event occurs. The latency
is the same for one or two cycle instructions. Individual
interrupt flag bits are set, regardless of the status of
their corresponding mask bit or the GIE bit.
Note:
Individual interrupt flag bits are set, regard-
less of the status of their corresponding
mask bit or the GIE bit.
Note:
If an interrupt occurs while the Global
Interrupt Enable (GIE) bit is being cleared,
the GIE bit may unintentionally be re-
enabled by the user’s Interrupt Service
Routine (the RETFIE instruction). The
events that would cause this to occur are:
1.
An instruction clears the GIE bit while
an interrupt is acknowledged.
2.
The program branches to the inter-
rupt vector and executes the Interrupt
Service Routine.
3.
The Interrupt Service Routine com-
pletes the execution of the RETFIE
instruction. This causes the GIE bit to
be set (enables interrupts), and the
program returns to the instruction
after the one which was meant to dis-
able interrupts.
Perform the following to ensure that inter-
rupts are globally disabled:
LOOP BCF
INTCON, GIE
; Disable global
;
interrupt bit
BTFSC INTCON, GIE
; Global interrupt
;
disabled?
GOTO
LOOP
; NO, try again
:
;
Yes, continue
;
with program
;
flow
745cov.book Page 107 Wednesday, August 2, 2000 8:24 AM
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