参数资料
型号: PIC16F1527-E/MR
厂商: Microchip Technology
文件页数: 19/94页
文件大小: 0K
描述: MCU 28KB FLASH 1536B RAM 64-QFN
标准包装: 40
系列: PIC® XLP™ 16F
核心处理器: PIC
芯体尺寸: 8-位
速度: 20MHz
连通性: I²C,LIN,SPI,UART/USART
外围设备: 欠压检测/复位,POR,PWM,WDT
输入/输出数: 54
程序存储器容量: 28KB(16K x 14)
程序存储器类型: 闪存
RAM 容量: 1.5K x 8
电压 - 电源 (Vcc/Vdd): 2.3 V ~ 5.5 V
数据转换器: A/D 30x10b
振荡器型: 内部
工作温度: -40°C ~ 125°C
封装/外壳: 64-VFQFN 裸露焊盘
包装: 管件
188
7810C–AVR–10/12
Atmel ATmega328P [Preliminary]
Bit 5 – UDREn: USART Data Register Empty
The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn
is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a
Data Register Empty interrupt (see description of the UDRIEn bit). UDREn is set after a reset to
indicate that the Transmitter is ready.
Bit 4 – FEn: Frame Error
This bit is set if the next character in the receive buffer had a Frame Error when received. I.e.,
when the first stop bit of the next character in the receive buffer is zero. This bit is valid until the
receive buffer (UDRn) is read. The FEn bit is zero when the stop bit of received data is one.
Always set this bit to zero when writing to UCSRnA.
Bit 3 – DORn: Data OverRun
This bit is set if a Data OverRun condition is detected. A Data OverRun occurs when the receive
buffer is full (two characters), it is a new character waiting in the Receive Shift Register, and a
new start bit is detected. This bit is valid until the receive buffer (UDRn) is read. Always set this
bit to zero when writing to UCSRnA.
Bit 2 – UPEn: USART Parity Error
This bit is set if the next character in the receive buffer had a Parity Error when received and the
Parity Checking was enabled at that point (UPMn1 = 1). This bit is valid until the receive buffer
(UDRn) is read. Always set this bit to zero when writing to UCSRnA.
Bit 1 – U2Xn: Double the USART Transmission Speed
This bit only has effect for the asynchronous operation. Write this bit to zero when using syn-
chronous operation.
Writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively dou-
bling the transfer rate for asynchronous communication.
Bit 0 – MPCMn: Multi-processor Communication Mode
This bit enables the Multi-processor Communication mode. When the MPCMn bit is written to
one, all the incoming frames received by the USART Receiver that do not contain address infor-
mation will be ignored. The Transmitter is unaffected by the MPCMn setting. For more detailed
19.10.3
UCSRnB – USART Control and Status Register n B
Bit 7 – RXCIEn: RX Complete Interrupt Enable n
Writing this bit to one enables interrupt on the RXCn Flag. A USART Receive Complete interrupt
will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG is
written to one and the RXCn bit in UCSRnA is set.
Bit
7
6
5
4
321
0
RXCIEn
TXCIEn
UDRIEn
RXENn
TXENn
UCSZn2
RXB8n
TXB8n
UCSRnB
Read/Write
R/W
R
R/W
Initial Value
0
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