参数资料
型号: PIC16F676-E/SL
元件分类: 微控制器/微处理器
英文描述: 8-BIT, FLASH, 20 MHz, RISC MICROCONTROLLER, PDSO14
封装: 3.90 MM, LEAD FREE, PLASTIC, SOIC-14
文件页数: 77/132页
文件大小: 1344K
代理商: PIC16F676-E/SL
2010 Microchip Technology Inc.
DS40039F-page 49
PIC16F630/676
7.2
A/D Acquisition Requirements
For the A/D converter to meet its specified accuracy,
the charge holding capacitor (CHOLD) must be allowed
to fully charge to the input channel voltage level. The
analog input model is shown in Figure 7-3. The source
impedance (RS) and the internal sampling switch (RSS)
impedance directly affect the time required to charge
the capacitor CHOLD. The sampling switch (RSS)
impedance varies over the device voltage (VDD), see
Figure 7-3. The maximum recommended imped-
ance for analog sources is 10 k
. As the impedance
is decreased, the acquisition time may be decreased.
After the analog input channel is selected (changed),
this acquisition must be done before the conversion
can be started.
To calculate the minimum acquisition time, Equation 7-1
may be used. This equation assumes that 1/2 LSb error
is used (1024 steps for the A/D). The 1/2 LSb error is the
maximum error allowed for the A/D to meet its specified
resolution.
To calculate the minimum acquisition time, TACQ, see
the PIC Mid-Range Reference Manual (DS33023).
EQUATION 7-1:
ACQUISITION TIME
FIGURE 7-3:
ANALOG INPUT MODEL
TACQ
TC
TACQ
=
Amplifier Settling Time +
Hold Capacitor Charging Time +
Temperature Coefficient
TAMP + TC + TCOFF
2
s + TC + [(Temperature -25°C)(0.05s/°C)]
CHOLD (RIC + RSS + RS) In(1/2047)
- 120pF (1k
+ 7k + 10k) In(0.0004885)
16.47
s
2
s + 16.47s + [(50°C -25C)(0.05s/C)
19.72
s
Note 1: The reference voltage (VREF) has no effect on the equation, since it cancels itself out.
2: The charge holding capacitor (CHOLD) is not discharged after each conversion.
3: The maximum recommended impedance for analog sources is 10 k
. This is required to meet the pin
leakage specification.
CPIN
VA
RS ANx
5 pF
VDD
VT = 0.6V
I LEAKAGE
RIC
1K
Sampling
Switch
SS RSS
CHOLD
= DAC capacitance
VSS
6V
Sampling Switch
5V
4V
3V
2V
567 8 9 10 11
(k
)
VDD
= 120 pF
± 500 nA
Legend: CPIN
VT
I LEAKAGE
RIC
SS
CHOLD
= input capacitance
= threshold voltage
= leakage current at the pin due to
= interconnect resistance
= sampling switch
= sample/hold capacitance (from DAC)
various junctions
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